Renesas M16C/50 Series User Manual page 498

M16C/5L Group, M16C/56 Group
(1) 8-bit Data Transmit Timing (with a Parity Bit and 1 Stop Bit)
Transmit/receive
clock
1
TE bit in the
UiC1 register
0
1
TI bit in the
UiC1 register
0
High
CTSi
Low
TXDi
1
TXEPT bit in the
UiC0 register
0
1
IR bit in the
SiTIC register
0
i = 0 to 4
The above assumes the following:
• The PRYE bit in the UiMR register is 1 (parity enabled).
• The STPS bit in the UiMR register is 0 (1 stop bit).
• The CRD bit in the UiC0 register is 0 ( CTS / RTS enabled)
• The CRS bit in the UiC0 register is 0 ( CTS selected).
• The UiIRS bit in the UiC1 register is 1
(an interrupt request occurs when transmit completed)
(2) 9-bit Data Transmit Timing (with No Parity Bit and 2 Stop Bits)
Transmit/
receive clock
1
TE bit in the
UiC1 register
0
1
TI bit in the
UiC1 register
0
TXDi
1
TXEPT bit in the
UiC0 register
0
1
IR bit in the
SiTIC register
0
i = 0 to 4
The above assumes the following:
• The PRYE bit in the UiMR register is 0 (parity disabled).
• The STPS bit in the UiMR register is 1 (two stop bit).
• The CRD bit in the UiC0 register is 1 ( CTS / RTS disabled)
• The UiIRS bit in the UiC1 register is 0
(an interrupt request occurs when transmit buffer becomes empty)
Figure 21.8 Transmit Timing in UART Mode
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
The transmit/receive clock stops once because a high-level signal is applied to
the CTS pin when the stop bit is verified. The transmit/receive clock resumes
Tc
running as soon as a low-level signal is applied to the CTS pin.
Set the data in the UiTB register.
Start bit
ST
D0 D1 D2 D3 D4 D5
Tc
Set the data in the UiTB register.
Start bit
ST D0 D1 D2 D3 D4 D5 D6
Set to 0 by an interrupt request acknowledgment or by a program.
Data is transferred from the UiTB
register to the UARTi transmit register.
Parity
Stop
bit bit
D7 ST
D6 P SP D0 D1 D2
Set to 0 by an interrupt request acknowledgment or by a program.
Tc = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of UiBRG count source (f1SIO, f2SIO,
f8SIO, f32SIO)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set to UiBRG
Data is transferred from the UiTB register
to the UARTi transmit register.
Stop Stop
bit bit
D7 D8 SP SP ST D0 D1 D2
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of UiBRG count source (f1SIO, f2SIO,
f8SIO, f32SIO)
fEXT: Frequency of UiBRG count source (external clock)
n: Value set to UiBRG
21. Serial Interface UARTi (i = 0 to 4)
Pulse stops because the TE
bit is 0.
D7
D3 D4 D5 D6 P SP
D3 D4 D5 D6 D7 D8 SP SP
Page 461 of 803
ST
D0 D1
ST D0 D1