Advertisement
M16C/5L Group, M16C/56 Group
21.3.4
Special Mode 2 (UART2)
In special mode 2, the serial interface module allows serial communication between one master and
multiple slaves. The transmit/receive clock polarity and phase are selectable. Table 21.18 lists Special
Mode 2 Specifications.
Table 21.18
Special Mode 2 Specifications
Item
Data format
Transmit/receive clock
Transmit/receive control
Transmission start conditions
Reception start conditions
Interrupt request generation
timing
Error detection
Selectable functions
Note:
1.
If an overrun error occurs, the received data of the U2RB register will be undefined. The IR bit in the S2RIC
register does not change.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Character data length: 8 bits
•
Master mode
The CKDIR bit in the U2MR register = 0 (internal clock):
fj = f1SIO, f2SIO, f8SIO, f32SIO
n: Setting value of U2BRG register 00h to FFh
Controlled by I/O ports
To start transmission, satisfy the following requirements:
•
The TE bit in the U2C1 register is 1 (transmission enabled)
•
The TI bit in the U2C1 register is 0 (data present in U2TB register)
To start reception, satisfy the following requirements:
•
The RE bit in the U2C1 register is 1 (reception enabled)
•
The TE bit is 1 (transmission enabled)
•
The TI bit is 0 (data present in the U2TB register)
For transmit interrupt, one of the following conditions can be selected
•
The U2IRS bit in the U2C1 register is 0 (transmit buffer empty):
When transferring data from the U2TB register to the UART2 transmit register (at
start of transmission)
•
The U2IRS bit is 1 (transfer completed):
When the serial interface completed sending data from the UART2 transmit register
For receive interrupt
•
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
(1)
Overrun error
This error occurs if the serial interface starts receiving the next data before reading
the U2RB register and receives the 7th bit of the next data
•
CLK polarity selection
Whether transfer data is output/input at the rising or falling edge of the transfer clock
can be selected.
•
LBS first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7.
•
Continuous receive mode selection
Reception is enabled by reading the U2RB register
•
Serial data logic switching
Function to invert the logic value of the transmit/receive data.
•
Clock phase setting
Selectable from four combinations of transmit/receive clock polarities and phases.
21. Serial Interface UARTi (i = 0 to 4)
Specification
-------------------- -
(
2 n
fj
)
+
1
Page 482 of 803
Advertisement
