Renesas M16C/50 Series User Manual page 547

M16C/5L Group, M16C/56 Group
22.2.6 I2C0 Control Register 1 (S3D0)
I2C0 Control Register 1
b7 b6 b5 b4 b3 b2 b1
0 0
Do not use the bit managing instruction (read-modify-write instruction) to access the S3D0 register. Use
the MOV instruction to write to the S3D0 register.
SIM (Stop condition detect interrupt enable bit) (b0)
When the SIM bit is 1 (I
detected, the SCPIN bit in the S4D0 register becomes 1 (stop condition detect interrupt requested) and
the IR bit in the IICIC register becomes 1 (interrupt requested).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
S3D0
Bit Symbol Bit Name
Stop condition detect interrupt
SIM
enable bit
WIT Data receive interrupt enable bit
—
Reserved bits
(b3-b2)
SDAM Internal SDA output monitor bit
SCLM Internal SCL output monitor bit
ICK0
2
I C-bus system clock select bit
(Enabled when bits ICK4 to ICK2
in the S4D0 register are 000b)
ICK1
2
C-bus interrupt by stop condition detection enabled) and a stop condition is
22. Multi-master I
Address
02B6h
Function
2
0: I C-bus interrupt by stop condition detection
is disabled
2
1: I C-bus interrupt by stop condition detection
is enabled
When write,
2
0: I C-bus interrupt at the 8th clock is disabled
2
1: I C-bus interrupt at the 8th clock is enabled
When read, internal WAIT bit monitor
2
0: I C-bus interrupt by falling edge of ACK clock
2
1: I C-bus interrupt at the 8th clock
Set to 0
0: Logic 0 output
1: Logic 1 output
0: Logic 0 output
1: Logic 1 output
b7 b6
0 0: fIIC divided by 2
0 1: fIIC divided by 4
1 0: fIIC divided by 8
1 1: Should not be set
2
C-bus Interface
Reset Value
0011 0000b
RW
RW
RW
RW
RO
RO
RW
RW
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