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M16C/5L Group, M16C/56 Group
(1) Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4 bit
in the G1BCR0 register are all 0)
FFFFh
Base timer
0000h
OUTC1_ j pin
G1IRj bit
G1IRk bit
j = 0, 2, 4, 6; k = j + 1
m: G1POj register value
n: G1POk register value
G1IRj and G1IRk: Bits in the G1IR register
The above assumes the following:
⋅ The IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ The EOCj bit in the G1OER register is 0 (output enabled).
(2) When the base timer matches either of following registers, the base timer is reset:
(a) G1PO0 register (when the RST1 bit is 1 and bits RST4 and RST2 are 0)
(b) G1BTRR register (when the RST4 bit is 1 and bits RST2 and RST1 are 0)
FFFFh
p + 1
Base timer
0000h
OUTC1_ j pin
G1IRj bit
G1IRk bit
When (a), j = 2, 4, 6. When (b), j = 0, 2, 4, 6.
k = j + 1
m: G1POj register value
p: Either G1PO0 or G1BTRR register value
G1IRj and G1IRk: Bits in the G1IR register
The above assumes the following:
⋅ The IVL bit in the G1POCRj register is 0 (output low as default) and the INV bit is 0 (output is not inverted).
⋅ The EOCj bit in the G1OER register is 0 (output enabled).
Figure 18.18 Operation Example in SR Waveform Output Mode
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
n
m
n - m
fBT1
Output high
To set this bit to 0,
write 0 by a program
n
m
n - m
fBT1
Output high
p + 2
fBT1
To set this bit to 0,
write 0 by a
program
65536 - n + m
fBT1
Output high
65536
fBT1
To set this bit to 0,
write 0 by a program
p + 2 - n + m
fBT1
Output high
To set this bit to 0,
write 0 by a program
Output low
Output low
Output high
Page 391 of 803
18. Timer S
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