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M16C/5L Group, M16C/56 Group
CPU clock
Dedicated 125 kHz on-chip
oscillator for the watchdog timer
Internal reset signal
(low active)
Bits WDTRCS1 and WDTRCS0
A write to the WDTR register
CSPRO: Bit in the CSPR register
WDC7: Bit in the WDC register
PM12: Bit in the PM1 register
CM07: Bit in the CM0 register
WDTUFS1, WDTUFS0, WDTRCS1, and WDTRCS0: Bits in the OFS2 address
Note:
1. When the CSPRO bit is 1 (the count source protect mode enabled):
The values set by bits WDTUFS0 and WDTUFS1 are set
When the CSPRO bit is 0 (the count source protect mode disabled): 7FFFh
Figure 13.1
Watchdog Timer Block Diagram
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Prescaler
CM07 = 0,
WDC7 = 0
1/16
CSPRO = 0
1/128
CM07 = 0,
WDC7 = 1
1/2
CM07 = 1
fWDT
CSPRO
Refresh period
control circuit
Watchdog timer counter
(See Note 1)
CSPRO = 1
13. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog timer reset
Page 200 of 803
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