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M16C/5L Group, M16C/56 Group
Table 21.14
Registers Used and Settings in I
Register
Bits
OCOSEL0
UCLKSEL0
PCLKR
PCLK1
0 to 7
U2TB
8
0 to 7
8
U2RB
ABT
OER
13 to 15
U2BRG
0 to 7
SMD2 to
SMD0
CKDIR
U2MR
4 to 6
IOPOL
CLK1, CLK0
CRS
TXEPT
U2C0
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2C1
UjIRS
UjRRM,
UiLCH,
UiERE
IICM
ABC
U2SMR
BBS
3 to 7
Note:
1.
This table does not describe a procedure.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
Master
Select clock prior to division for UART0 to
UART2.
Select the count source for the U2BRG
register.
When transmitting, set the transmission
data. When receiving, set FFh.
When transmitting, set to 1. When
receiving, set the value in the ACK bit.
Reception data can be read.
ACK or NACK is set in this bit.
Arbitration lost detection flag
Overrun error flag
When read, the read value is undefined.
Set a bit rate.
Set to 010b.
Set to 0.
Set to 0.
Set to 0.
Select the count source for the UiBRG
register.
Disabled because CRD is 1
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 0.
Set to 1.
Select the timing that arbitration lost is
detected.
Bus busy flag
Set to 0.
21. Serial Interface UARTi (i = 0 to 4)
(1)
C Mode (1/2)
Function
Select clock prior to division for UART0 to
UART2.
Select the count source for the U2BRG
register.
When transmitting, set the transmission
data. When receiving, set FFh.
When transmitting, set to 1. When receiving,
set the value in the ACK bit.
Reception data can be read.
ACK or NACK is set in this bit.
Disabled
Overrun error flag
When read, the read value is undefined.
Disabled
Set to 010b.
Set to 1.
Set to 0.
Set to 0.
Disabled
Disabled because CRD is 1
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Reception complete flag
Set to 1.
Set to 0.
Set to 1.
Disabled
Bus busy flag
Set to 0.
Slave
Page 469 of 803
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