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M16C/5L Group, M16C/56 Group
17.3.1.5
Simultaneous Conduction Prevention
This function prevents the upper and lower output signals from being active simultaneously due to
program errors or unexpected program operation. When the high- and low-side output signals
become active at the same time while the simultaneous conduction is disabled by the INV04 bit in the
INVC0 register, the following occur:
•
The INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled).
•
The INV05 bit in the INVC0 register becomes 1 (simultaneous conduction detected).
Pins U, U , V, V , W, and W become high-impedance.
•
17.3.1.6
Three-Phase PWM Waveform Output Pins
Pins U, U , V, V , W, and W output a PWM waveform under the following conditions:
•
The INVC02 bit in the INVC0 register is 1 (three-phase motor control timer function).
•
The INVC03 bit in the INVC0 register is 1 (three-phase motor control timer output enabled).
•
Bits PFC5 to PFC0 in the PFCR register are 1 (three-phase PWM output (selected independently
for each pin)).
The three-phase output forced cutoff by the SD pin is available.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
17. Three-Phase Motor Control Timer Function
Page 321 of 803
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