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M16C/5L Group, M16C/56 Group
18.2.15 Timer S I/O Control Register 1 (G1IOR1)
Timer S I/O Control Register 1
b7 b6 b5 b4
b3
b2
b1
The value written to this register is reflected to the internal circuit when the clock is synchronized with
the base timer count source (fBT1).
Set the corresponding output control bits IOj1 and IOj0 to 00b for the input channels determined by
setting the FSCj bit (j = 4 to 7) in the G1FS register to 1 (time measurement function is selected).
In SR waveform output mode, set bits IOj1 and IOj0 to 00b for both odd and even channels.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
G1IOR1
Bit Symbol
Bit Name
IO40
OUTC1_4 output control bit
IO41
IO50
OUTC1_5 output control bit
IO51
IO60
OUTC1_6 output control bit
IO61
IO70
OUTC1_7 output control bit
IO71
Address
02EFh
Function
b1 b0
0 0: Outputs high or low, depending on the
mode selected by bits MOD1 and MOD0 in
the G1POCR4 register.
0 1: Output low by compare match with the
G1PO4 register.
1 0: Outputs high by compare match with the
G1PO4 register.
1 1: Do not set.
b3 b2
0 0: Outputs high or low, depending on the
mode selected by bits MOD1 and MOD0 in
the G1POCR5 register.
0 1: Outputs low by compare match with the
G1PO5 register.
1 0: Outputs high by compare match with the
G1PO5 register.
1 1: Do not set.
b5 b4
0 0: Outputs high or low, depending on the
mode selected by bits MOD1 and MOD0 in
the G1POCR6 register.
0 1: Outputs low by compare match with the
G1PO6 register.
1 0: Outputs high by compare match with the
G1PO6 register.
1 1: Do not set.
b7 b6
0 0: Outputs high or low, depending on the
mode selected by bits MOD1 and MOD0 in
the G1POCR7 register.
0 1: Outputs low by compare match with the
G1PO7 register.
1 0: Outputs high by compare match with the
G1PO7 register.
1 1: Do not set.
18. Timer S
Reset Value
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
Page 364 of 803
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