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M16C/5L Group, M16C/56 Group
24.3
Operations
24.3.1
A/D Conversion Cycle
A/D conversion cycle is based on fAD and φ AD. Divide fAD so φ AD conforms the standard frequency.
Figure 24.2 shows fAD and φ AD.
CKS3
0
f1
fOCO40M
1
CKS0: Bit in the ADCON0 register
CKS1: Bit in the ADCON1 register
CKS2, CKS3: Bits in the ADCON2 register
fAD and φ AD
Figure 24.2
Figure 24.3 shows A/D Conversion Timing.
Start
processing
Start
processing
Processing
1 to 2
cycle
fAD
The above figure applies under the following conditions:
One-shot mode
φAD = fAD
Figure 24.3
A/D Conversion Timing
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
CKS2
0
fAD
1/3
fAD
1
Open-circuit
First bit conversion time
detection
Open-circuit
Sampling time
detection
charge time
2 φAD
15 φAD
40 φAD
42 φAD
Select A/D conversion speed
1
0
1/2
1/2
CKS0
Second
Third bit
bit
Compare
Compare
Compare
time
time
time
25 φAD
24. A/D Converter
CKS1
1
φAD
0
End
Tenth bit
processing
Compare
End
time
processing
2 to 3
fAD
Page 625 of 803
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