Renesas M16C/50 Series User Manual page 241

M16C/5L Group, M16C/56 Group
13.2.4 Watchdog Timer Start Register (WDTS)
Watchdog Timer Start Register
b7
The WDTS register is enabled when the WDTON bit in the OFS1 address is 1 (watchdog timer stops
after reset).
13.2.5 Watchdog Timer Control Register (WDC)
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
WDTS
The watchdog timer starts counting after a write instruction to this register.
Symbol
b0
WDC
Bit Symbol Bit Name
WDC0
WDC1
Bits b10 to b5 can be read when the count source protection mode is
disabled.
WDC2
When the count source protection mode is enabled, while bits WDTUFS1
and WDTUFS0 in the OFS2 address are:
00b (03FFh), bits b5 to b0 can be read
WDC3
01b (0FFFh), bits b8 to b3 can be read
10b (1FFFh), bits b9 to b4 can be read
11b (3FFFh), bits b10 to b5 can be read
WDC4
WDC5
—
Reserved bit
(b6)
WDC7 Prescaler select bit
Address
037Eh
Function
Address
037Fh
Function
The read value is 0.
0: Divided by 16
1: Divided by 128
13. Watchdog Timer
Reset Value
XXh
RW
WO
Reset Value
00XX XXXXb
RW
RO
RO
RW
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