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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
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302
Three-Phase Motor Control Timer
Chap. 17 Changed "Three-Phase Motor Control Timer" to "Three-Phase Motor Control Timer Function".
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325
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343
Timer S
Chap. 18. Changed the configuration, and added detailed explanations.
Chap. 18.
Chap. 18. Specified the internal circuit as the place to reflect a value written to the GT bit when the clock is
Chap. 18.
Chap. 18. Added legends where i, j, or k is used to indicate its value.
Chap. 18. Changed "single-waveform" to "single-phase waveform".
345, 346 Figure 18.1 IC/OC Block Diagram (1/2) and Figure 18.2 IC/OC Block Diagram (2/2): Added details.
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M16C/5L, M16C/56 Group User's Manual: Hardware
Table 16.9 Specifications of Pulse Period/Pulse Width Measurement Modes:
• Moved previous note 3 to the description for TBiS above notes.
• Added note 3.
Table 16.10 Registers and Settings in Pulse Period/Pulse Width Measurement Modes:
Modified "TBCS0 to TBCS3" to "TBCS0 to TBCS1" in the Register column.
16.5 Notes on Timer B: Rewritten by common items, and each mode.
Table 17.1 Three-Phase Motor Control Timer Function Specifications: Changed "Three-phase
waveform output pins" to "Three-phase PWM waveform output pins" in the Item column.
Table 17.8 Three-Phase Mode 0 Specifications:
Modified the description in the parenthesis in the Timer B2 interrupt row.
Table 17.15 Sawtooth Wave Modulation Mode Specifications:
Modified the description in the parenthesis in the Timer B2 interrupt row.
17.5.2 Influence of SD : Changed the title from "Forced Cutoff Input" and changed the explanation.
Changed terminologies in this chapter are as follows:
• "digital debounce function" to "digital debounce filter"
• Remove the term "mode" from increment, increment/decrement, and two-phase pulse signal
processing.
• "channel interrupt" to "IC/OC channel interrupt"
• "base timer interrupt" to "IC/OC base timer interrupt"
• Appropriate explanations/names are provided for base timer reset depending on its condition.
• "fBT1 clock cycles" to "fBT1 cycles"
synchronized with the base timer count source (fBT1).
Added pin names for two-phase clock input.
Accordingly, changed "P8_0" and "P8_1" to "TSUDA" and "TSUDB", respectively.
Table 18.2 I/O Pins:
• Added pins TSUDA, TSUDB, and INT1 .
• Added note 1 and note 2.
18.2.2 Waveform Generation Register j (G1POj) (j = 0 to 7):
• Specified the internal buffer as the place to reflect the value written to the G1POj register.
• Added details.
18.2.3 Waveform Generation Control Register j (G1POCRj) (j = 0 to 7):
• Changed the explanation of bits MOD1 and MOD0.
• Changed "internal counter" to "buffer" in the sentence starting with "When writing a value to the
G1POj register..." in the RLD explanation.
18.2.4 Time Measurement Control Register j (G1TMCRj) (j = 0 to 7):
• Added some descriptions to the Function columns of bits DFS1 and DFS0, and the GOC bit.
• Changed the register explanation.
• Added explanations to bits DFS1 and DFS0, and the GSC bit.
18.2.5 Base Timer Register (G1BT):
• Changed the Function column in the register diagram.
• Changed the explanation since the write operation to this register is disabled.
• Added "the state is released" to the explanation for when the BTS bit is set to 1.
18.2.6 Base Timer Control Register 0 (G1BCR0):
• Rewrote the first and second paragraphs in the explanation for bits BCK1 and BCK0.
• Added the IT bit explanation.
18.2.7 Base Timer Control Register 1 (G1BCR1); Changed the following in the RST1 bit
explanation:
• Added "while the RST1 bit is 1" to the first sentence in the second paragraph.
• Changed the reference target.
• Deleted the explanation regarding the G1POj register and moved it to 18.2.2.
Description
Summary
C- 7
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