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M16C/5L Group, M16C/56 Group
Table 14.3
Sources of DMA Request (DMA0)
DSEL4 to DSEL0
DMS is 0 (Basic Source of Request) DMS is 1 (Expanded Source of Request)
Falling edge of the INT0 pin
0 0 0 0 0 b
0 0 0 0 1 b
Software trigger
0 0 0 1 0 b
Timer A0
0 0 0 1 1 b
Timer A1
0 0 1 0 0 b
Timer A2
0 0 1 0 1 b
Timer A3
0 0 1 1 0 b
Timer A4
0 0 1 1 1 b
Timer B0
0 1 0 0 0 b
Timer B1
0 1 0 0 1 b
Timer B2
0 1 0 1 0 b
UART0 transmission
0 1 0 1 1 b
UART0 reception
0 1 1 0 0 b
UART2 transmission
0 1 1 0 1 b
UART2 reception
0 1 1 1 0 b
A/D converter
0 1 1 1 1 b
UART1 transmission
1 0 0 0 0 b
UART1 reception
1 0 0 0 1 b
–
1 0 0 1 0 b
–
1 0 0 1 1 b
UART4 transmission
1 0 1 0 0 b
UART4 reception
1 0 1 0 1 b
UART3 transmission
1 0 1 1 0 b
UART3 reception
1 0 1 1 1 b
–
1 1 X X X b
–
X: 0 or 1
–: Do not set.
Table 14.4
Source of DMA Request (DMA1)
DSEL4 to DSEL0
DMS = 0 (Basic Source of Request) DMS = 1 (Expanded Source of Request)
Falling edge of the INT1 pin
0 0 0 0 0 b
0 0 0 0 1 b
Software trigger
0 0 0 1 0 b
Timer A0
0 0 0 1 1 b
Timer A1
0 0 1 0 0 b
Timer A2
0 0 1 0 1 b
Timer A3
0 0 1 1 0 b
Timer A4
0 0 1 1 1 b
Timer B0
0 1 0 0 0 b
Timer B1
0 1 0 0 1 b
Timer B2
0 1 0 1 0 b
UART0 transmission
0 1 0 1 1 b
UART0 reception
0 1 1 0 0 b
UART2 transmission
0 1 1 0 1 b
UART2 reception/ACK2
0 1 1 1 0 b
A/D converter
0 1 1 1 1 b
UART1 reception
1 0 0 0 0 b
UART1 transmission
1 0 0 0 1 b
–
1 0 0 1 0 b
–
1 0 0 1 1 b
UART4 transmission
1 0 1 0 0 b
UART4 reception4
1 0 1 0 1 b
UART3 transmission
1 0 1 1 0 b
UART3 reception
1 0 1 1 1 b
–
1 1 X X X b
–
X: 0 or 1
– Do not set.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
IC/OC base timer
–
IC/OC channel 0
IC/OC channel 1
–
–
Both edges of the INT0 pin
–
–
–
IC/OC channel 2
IC/OC channel 3
IC/OC channel 4
IC/OC channel 5
IC/OC channel 6
IC/OC channel 7
Falling edge of the INT4 pin
Both edges of the INT4 pin
–
–
–
–
–
–
–
IC/OC base timer
–
IC/OC channel 0
IC/OC channel 1
–
–
–
Both edges of the INT1 pin
–
–
IC/OC channel 2
IC/OC channel 3
IC/OC channel 4
IC/OC channel 5
IC/OC channel 6
IC/OC channel 7
Falling edge of the INT5 pin
Both edges of the INT5 pin
–
–
–
–
–
–
–
14. DMAC
Page 219 of 803
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