Advertisement
M16C/5L Group, M16C/56 Group
21.3.6
Special Mode 4 (SIM Mode) (UART2)
In this mode, the serial interface module allows SIM interface devices to communicate in UART mode.
Both direct and inverted formats are available. The TXD2 pin outputs a low-level signal when a parity
error is detected.
Table 21.22 lists the specifications of SIM mode. Table 21.23 lists the related registers and their
settings.
Table 21.22
SIM Mode Specifications
Item
Data formats
Transmit/receive clock
Transmission start
conditions
Reception start
conditions
Interrupt request
(2)
generation timing
Error detection
Notes:
1.
If an overrun error occurs, the received data of the U2RB register will be undefined. The IR bit in the
S2RIC register does not change.
2.
After reset is deasserted, a transmit interrupt request is generated by setting bits U2IRS and U2ERE
in the U2C1 register to 1 (transmission completed, error signal output), then setting the TE bit to 1
(transmission enabled) and the transmission data to the U2TB register. Therefore, when using SIM
mode, make sure to set the IR bit to 0 (interrupt not requested) after setting these bits.
3.
The timing at which the framing error flag and the parity error flag are set is detected when data is
transferred from the UART2 receive register to the U2RB register.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
•
Direct format
•
Inverted format
•
The CKDIR bit in the U2MR register is 0 (internal clock): fi/(16(n + 1))
fi = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of the U2BRG register 00h to FFh
•
The CKDIR bit is 1 (external clock): fEXT/(16(n + 1))
fEXT = input from the CLK2 pin
n = setting value of the U2BRG register 00h to FFh
To start transmission, satisfy the following requirements:
•
The TE bit in the U2C1 register is 1 (transmission enabled)
•
The TI bit in the U2C1 register is 0 (data present in the U2TB register)
To start reception, satisfy the following requirements:
•
The RE bit in the U2C1 register is 1 (reception enabled)
•
Start bit detection
•
While transmitting
When the serial interface completes transmitting data from the UART2
transmit register (the U2IRS bit is 1)
•
While receiving
When transferring data from the UART2 receive register to the U2RB register
(at completion of reception)
•
(1)
Overrun error
This error occurs if the serial interface starts receiving the next data before
reading the U2RB register and receives the bit before the last stop bit of the
next data.
•
(3)
Framing error
This error occurs when the number of stop bits set is not detected.
(3)
•
Parity error
During reception, if a parity error is detected, a parity error signal is output from
the TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2
pin when a transmission interrupt occurs.
•
Error sum flag
This flag becomes 1 when an overrun, framing, or parity errors occurs.
21. Serial Interface UARTi (i = 0 to 4)
Specification
Page 488 of 803
Advertisement
