Renesas M16C/50 Series User Manual page 410

M16C/5L Group, M16C/56 Group
(1) The base timer is reset while it is incrementing.
TSUDA (A-phase)
Input
waveform
TSUDB (B-phase)
fBT1
INT1 (Z-phase)
Counter value
(2) The base timer is reset while it is decrementing.
TSUDA (A-phase)
Input
waveform
TSUDB (B-phase)
fBT1
INT1 (Z-phase)
Counter value
The above assumes the following:
• The RST2 bit in the G1BCR1 register is 1 (base timer is reset by applying low to the INT1 pin).
• The G1DV register is 00b (no division).
Note:
1. The INT1 pin should be driven low for at least 1.5 fBT1 cycles.
Figure 18.7 Two-Phase Pulse Signal Processing (When Using the Base Timer Reset)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
(Note 1)
m m + 1 0000h
Counter becomes 0000h at this timing. Counter becomes 0001h at this timing.
(Note 1)
m m - 1 0000h
Counter becomes 0000h at this timing.
18. Timer S
0001h 0002h
FFFFh FFFEh
Counter becomes FFFFh at this timing.
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