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M16C/5L Group, M16C/56 Group
Table 21.20
Registers Used and Settings in Special Mode 2
Register
UCLKSEL0
OCOSEL0
PCLKR
U2TB
U2RB
8, 11, 13 to 15
U2BRG
SMD2 to SMD0
U2MR
CLK0, CLK1
U2C0
U2C1
U2SMR
U2SMR2
U2SMR3
0, 2, 4 to 7
U2SMR4
Notes:
1.
This table does not describe a procedure.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bits
Select clock prior to division for UART0 to UART2.
PCLK1
Select the count source for the U2BRG register.
0 to 7
Set transmission data.
8
- (does not need to be set) If necessary, set to 0.
0 to 7
Reception data can be read.
OER
Overrun error flag
When read, the read value is undefined.
0 to 7
Set bit rate.
Set to 001b.
CKDIR
Set to 0.
4 to 6
Set to 0.
IOPOL
Set to 0.
Select the count source for the U2BRG register.
CRS
Disabled because CRD is 1
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Select TXD2 pin output format.
Clock phases can be set in combination with the CKPH bit in the
CKPOL
U2SMR3 register.
UFORM
Select the LSB first or MSB first.
TE
Set to 1 to enable transmission/reception.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
U2IRS
Select UART2 transmit interrupt source.
U2RRM
Set to 1 to use continuous receive mode.
U2LCH
Set to 1 to use inverted data logic.
U2ERE
Set to 0.
0 to 7
Set to 0.
0 to 7
Set to 0.
Clock phases can be set in combination with the CKPOL bit in the
CKPH
U2C0 register.
NODC
Set to 0.
Set to 0.
0 to 7
Set to 0.
21. Serial Interface UARTi (i = 0 to 4)
(1)
Function
Page 484 of 803
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