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M16C/5L Group, M16C/56 Group
23.1.12.3 TFFST Bit
The TFFST bit is set to 1 (transmit FIFO is full) when the number of unsent messages in the transmit
FIFO is 4. This bit is set to 0 (transmit FIFO is not full) when the number of unsent messages in the
transmit FIFO is less than 4. This bit is set to 0 when transmission from the transmit FIFO has been
aborted.
23.1.12.4 TFEST Bit
The TFEST bit is set to 1 (no message in transmit FIFO) when the number of unsent messages in the
transmit FIFO is 0. This bit is set to 1 when transmission from the transmit FIFO has been aborted.
The TFEST bit is set to 0 (message in transmit FIFO) when the number of unsent messages in the
transmit FIFO is not 0.
Figure 23.15 shows the transmit FIFO mailbox operation.
CAN bus
Internal bus
TFEST
TFFST
CAN0 transmit FIFO interrupt
Bits 25 to 24 in C0MIER register = 01b
CAN0 transmit FIFO interrupt
Bits 25 to 24 in C0MIER register = 11b
C0TFPCR register
TFEST, TFFST: Bits in the C0TFCR register
Figure 23.15 Transmit FIFO Mailbox Operation (Bits 25 and 24 in C0MIER Register = 01b and 11b)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Transmit FIFO mailbox
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23. CAN Module
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