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M16C/5L Group, M16C/56 Group
1
(bus busy)
(See Note 1)
The above assumes the following:
XIN = 16 MHz, main clock divided by 1 (no division), U2BRG count source = f1
Note:
1. After a stop condition is generated, when generating the next start condition, after setting the STSPSEL bit in
the U2SMR4 register to 0 and waiting at least half a cycle of the SCL clock, then set the STAREQ bit to 1.
Technical update number: TN-16C-130A/EA
Figure 21.18 Register Setting Procedures for Condition Generation
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Start condition generation
BBS bit in the U2SMR
register is 1 ?
0 (bus free)
U2SMR4 ← 70h
U2MR ← 02h
U2BRG ← 0
U2SMR2 ← 03h
U2BRG ← IIC_BAUDRATE
U2SMR4 ← 71h
U2SMR4 ← 09h
End
Restart condition generation
U2SMR4 ← 02h
U2SMR4 ← 3Ah
End
Stop condition generation
U2SMR4 ← 04h
U2SMR4 ← 3Ch
End
21. Serial Interface UARTi (i = 0 to 4)
Wait for bus release.
Set the STSPSEL bit to 0.
2
Select I
C mode and internal clock .
Set the U2BRG register to 00h.
Executing this command requires at least half a cycle of
the SCL clock (62.5 ns).
Reset the U2BRG value to target bit rate.
Set the STAREQ bit to 1.
Set the STSPSEL bit to 1.
Set the RSTAREQ bit to 1.
Set the STSPSEL bit to 1.
Set the STPREQ bit to 1.
Set the STSPSEL bit to1.
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