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M16C/5L Group, M16C/56 Group
18.3.3.2
Inverted Waveform Output Mode
The output level at the OUTC1_j pin is inverted every time the base timer value matches the G1POj
register value (j = 0 to 7). When bits MOD1 and MOD0 in the G1POCRj register are 10b (inverted
waveform output mode), set bits UD1 and UD0 in the G1BCR1 register to 00b (increment) or 01b
(increment/decrement).
Table 18.14 lists the specifications of inverted waveform output mode. Figure 18.16 and Figure 18.17
show the operational examples of inverted waveform output mode.
Table 18.14
Inverted Waveform Output Mode Specifications
Item
Output waveform
Waveform output start
condition
Waveform output stop
condition
Interrupt request
occurrence timing
OUTC1_j pin
Selectable functions
j = 0 to 7
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
•
Free-running operation (when bits RST2 and RST1 in the G1BCR1 register and the RST4
bit in the G1BCR0 register are all 0 (the base timer is not reset))
×
65536 2
Cycle:
------------------------- -
fBT1
65536
High or low width:
--------------- -
fBT1
•
When the base timer matches either of the following registers, the base timer is set to
0000h:
•
G1PO0 register (when the RST1 bit is 1, and bits RST4 and RST2 are 0)
•
G1BTRR register (when the RST4 bit is 1, and bits RST2 and RST1 are 0)
(
)
2 n
+
2
Cycle:
-------------------- -
fBT1
n
+
High or low width:
------------ -
fBT1
m: G1POj register setting value
n: G1PO0 register or G1BTRR register setting value
0000h ≤ m < n ≤ FFFDh
Set the IFEj bit in the G1FE register to 1 (channel j function enabled).
Set the IFEj bit to 0 (channel j function disabled).
When the base timer value matches the G1POj register value.
Pulse output or I/O port
•
Default value setting
Select the starting waveform output level.
•
Output level inversion
Select if the waveform level output from the OUTC1_j pin is inverted.
•
Compare match output function
When the compare match output function is set, the output level is fixed to high or low from
when the base timer value matches the G1POj register value.
When the compare match output function is disabled, an inverted waveform is output again
from the next compare match timing.
•
Output disabled function
When the EOCj bit in the G1OER register is 1 (output disabled), the OUTC1_j pin stops
waveform output and becomes a programmable I/O port. When the EOCj bit is 0 (output
enabled), the OUTC1_j pin outputs inverted waveform again.
Specification
2
18. Timer S
Page 385 of 803
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