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M16C/5L Group, M16C/56 Group
15.3.4.3
Counter Initialization Using Two-Phase Pulse Signal Processing
This function initializes the timer count value to 0000h using Z-phase (counter initialization) input
during two-phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal
processing, free-running type, multiply-by-4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing 0000h to the TA3 register and setting the
TAZIE bit in the ONSF register to 1 (Z-phase input enabled).
Counter initialization is accomplished by Z-phase input edge detection. The rising or falling edge can
be selected as the active edge by setting the POL bit in the INT2IC register. The Z-phase pulse width
must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after accepting Z-phase input. Figure 15.9 shows
the Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase.
When timer A3 overflow or underflow coincides with counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT input
(A-phase)
TA3IN input
(B-phase)
Count source
(1)
ZP input
(Z-phase)
Timer A3
Note:
1. This timing diagram assumes when the POL bit in the INT2IC register is 1 (rising edge).
Figure 15.9
Relationship between the Two-Phase Pulse (A-Phase and B-Phase) and the Z-Phase
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Input pulse for one clock cycle of the count
source or greater.
m
m + 1
1
2
3
4
15. Timer A
5
Page 260 of 803
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