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M16C/5L Group, M16C/56 Group
14.3
Operations
14.3.1
DMA Enabled
When data transfer starts after setting the DMAE bit in the DMiCON register to 1 (enabled), the DMAC
operates as listed below (i = 0 to 3). If 1 is written to the DMAE bit when it is already set to 1, the DMAC
also performs the following operations.
•
The forward address pointer is reloaded with the SARi register value when the DSD bit in the
DMiCON register is 1 (forward), or the DARi register value when the DAD bit in the DMiCON
register is 1 (forward).
•
The DMAi transfer counter is reloaded with the DMAi transfer counter reload register value.
14.3.2
DMA Request
The DMAC can generate a DMA request as triggered by the request source that is selected with the
DMS bit and bits DSEL4 to DSEL0 in the DMiSL register (i = 0 to 3) on each channel. Table 14.7 lists
the Timing at Which the DMAS Bit Value Changes.
When a DMA request is generated, the DMAS bit becomes 1 (DMA requested) regardless of the DMAE
bit status. If the DMAE bit is 1 (enabled) when this occurs, the DMAS bit becomes 0 (DMA not
requested) immediately before a data transfer starts. This bit cannot be set to 1 by a program (writing 1
has no effect).
If the DMAE bit is 1, data transfers start immediately after a DMA request is generated, so the DMAS bit
in almost all cases is 0 when read in a program. Read the DMAE bit to determine whether the DMAC is
enabled. When a DMA request transfer cycle is shorter than the DMA transfer cycle, the number of
transfer requests and the number of transfers do not match.
When a peripheral function is selected as the DMA source, relations with the interrupt control registers
are as follows:
•
DMA transfers are not affected by the I flag or interrupt control registers. DMA requests are always
accepted even when interrupt requests are not accepted.
•
The IR bit in the interrupt control register retains its value when a DMA transfer is accepted.
Table 14.7
Timing at Which the DMAS Bit Value Changes
DMA Source
Software trigger
External source
Peripheral function
i = 0 to 3
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Timing at which the bit becomes 1
When the DSR bit in the DMiSL register
is set to 1.
When an input edge of pins INT0 to
INT5 matches with what is selected by
setting bits DSEL4 to DSEL0 and DMS
in the DMiSL register.
When an interrupt request is generated
by the peripheral function selected by
setting the DMS bit and bits DSEL4 to
DSEL0 in the DMiSL register.(If the IR
bit in an interrupt control register is 0,
the timing is when the IR bit becomes
1.)
DMAS Bit in the DMiCON Register
Timing at which the bit becomes 0
•
Immediately before a data transfer
starts
•
When set to 0 by a program
14. DMAC
Page 221 of 803
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