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M16C/5L Group, M16C/56 Group
1.5
Pin Assignments
Figure 1.5 shows the pin assignments for 80-pin package and Figure 1.6 shows the pin assignments for
64-pin package.
P0_6 / AN0_6
P0_5 / AN0_5
P0_4 / AN0_4
P0_3 / AN0_3
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
AVSS
P10_0 / AN_0
VREF
AVCC
P9_7 / AN2_7 / RXD4
P9_6 / AN2_6 / TXD4
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5L Group.
Figure 1.5
Pin Assignment for 80-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 011b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
61
62
63
64
M16C/5L Group
65
66
67
M16C/56 Group
68
69
70
71
PLQP0080KB-A
72
73
(80P6Q-A)
74
75
(Top view)
76
77
78
79
80
P6_3 / TXD0
40
P3_0 / CLK3
39
P3_1 / RXD3
38
P3_2 / TXD3
37
P3_3 / CTS3 / RTS3
36
P3_4
35
P3_5
34
P3_6
33
P3_7
32
P6_4 / CTS1 / RTS1
31
P6_5 / CLK1
30
P6_6 / RXD1
29
P6_7 / TXD1
28
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
27
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
26
P7_2 / CLK2 / TA1OUT / V / RXD1
25
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
24
P7_4 / TA2OUT / W
23
P7_5 / TA2IN / W
22
21
P7_6 / TA3OUT
1. Overview
Page 10 of 803
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