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M16C/5L Group, M16C/56 Group
9.3.4
Stop Mode
In stop mode, all oscillator are stopped, so the CPU clock and peripheral function clocks are also
stopped. Therefore, the CPU and the peripheral functions using these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to pin VCC is VRAM or greater, the
contents of internal RAM are retained. When applying 3.0 V or less to pin VCC, make sure VCC ≥
VRAM.
However, the peripheral functions activated by external signals keep operating.
9.3.4.1
Entering Stop Mode
The MCU enters stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks turned off). At
the same time, the CM06 bit in the CM0 register becomes 1 (divide-by-8 mode), and the CM15 bit in
the CM1 register becomes 1 (main clock oscillator drive capability high).
Before entering stop mode, set the CM20 bit to 0 (oscillator stop/restart detect function disabled).
When the CM11 bit is 1 (PLL clock used as the CPU clock source), set the CM11 bit to 0 (main clock
used as the CPU clock source), and then the PLC07 bit to 0 (PLL turned off) before entering stop
mode.
When using stop mode, set the following:
(1) Set the I flag to 0.
(2) Set the interrupt priority level of bits ILVL2 to ILVL0 in the interrupt control register for the
peripheral function interrupt which is used to exit stop mode. Start the peripheral function which
is used to stop mode if it is stopped.
(3) Set 000b (interrupt disabled) to bits ILVL2 to ILVL0 in the interrupt control registers for the
peripheral function interrupts not used to exit stop mode.
(When using any of the following resets or interrupts to exit stop mode, set 000b to bits ILVL2 to
ILVL0 in all interrupt control registers for peripheral function interrupts: hardware reset, voltage
monitor 0 reset, NMI interrupt, or voltage monitor 2 interrupt)
(4) Set the I flag to 1.
(5) Set the CM10 bit in the CM1 register to 1.
When using the NMI interrupt to exit stop mode, set the NDDR register to FFh before setting the
CM10 bit to 1. When using the INT5 interrupt to exit stop mode, set the P17DDR register to FFh
before setting the CM10 bit to 1.
9.3.4.2
Pin Status in Stop Mode
Table 9.8 lists Pin Status in Stop Mode.
Table 9.8
Pin Status in Stop Mode
Pin
I/O ports
CLKOUT
XOUT
XCIN, XCOUT
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Maintains the pin state immediately before entering stop mode
High
High
High-impedance
9. Power Control
Pin State
Page 131 of 803
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