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M16C/5L Group, M16C/56 Group
21.2.1
UART Clock Select Register (UCLKSEL0)
UART Clock Select Register
b7
b6 b5 b4
b3
b2
b1
0
OCOSEL0 (UART0 to UART2 clock prior to division select bit) (b2)
OCOSEL1 (UART3 to UART4 clock prior to division select bit) (b3)
Set bits OCOSEL0 and OCOSEL1 while transmission/reception of UART0 to UART2 and UART3 to
UART4 stops.
Set the OCOSEL0 or OCOSEL1 bit before setting other registers associated with UART0 to UART2
and UART3 to UART4. After changing the OCOSEL0 or OCOSEL1 bit, set other registers associated
with UART0 to UART2 and UART3 to UART4 again.
21.2.2
Peripheral Clock Select Register (PCLKR)
Peripheral Clock Select Register
b7
b6 b5 b4
b3
b2
b1
0
0
0
0
0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
0
UCLKSEL0
Bit Symbol
Bit Name
—
Reserved bits
(b1-b0)
UART0 to UART2 clock prior
OCOSEL0
to division select bit
UART3 to UART4 clock
OCOSEL1
prior to division select bit
—
No register bits. If necessary, set to 0. The read value is undefined.
(b7-b4)
Symbol
b0
PCLKR
Bit Symbol
Bit Name
Timers A, B, S, multi-master I
interface clock select bit
PCLK0
(clock source for timers A , B, S,
dead time timer, and multi-master
2
I
C-bus interface)
SI/O clock select bit
PCLK1
(clock source for UART0 to
UART4)
—
Reserved bits
(b4-b2)
PCLK5
Clock output function extension bit
—
Reserved bits
(b7-b6)
21. Serial Interface UARTi (i = 0 to 4)
Address
0252h
Function
Set to 0
0 : f1
1 : fOCO-F
0 : f1
1 : fOCO-F
Address
0012h
Function
2
C-bus
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
0: f2SIO
1: f1SIO
Set to 0.
0: Selected by setting bits CM01 and CM00 in
the CM0 register
1: Outputs f1
Set to 0.
Reset Value
X0h
RW
RW
RW
RW
—
Reset Value
00000011b
RW
RW
RW
RW
RW
RW
Page 436 of 803
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