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M16C/5L Group, M16C/56 Group
28.5.2.3
Signal Line Whose Level Changes at a High-Speed
For a signal line whose level changes at a high-speed, wire it as far away from the crystal/ceramic
resonator and its wiring pattern as possible. Do not wire it across or extend it parallel to a clock-
related signal line or other signal lines which are sensitive to noise.
Reason:
A signal whose level changes at a high-speed (such as the signal from the TAiOUT pin) affects other
signal lines due to the level change at rising or falling edges. Specifically, when the signal line
crosses the clock-related signal line, the clock waveform becomes unstable, which causes an error in
operation or a program runaway.
Figure 28.6
Wiring of Signal Line Whose Level Changes at High-Speed
28.5.3
CPU Clock
(Technical update number: TN-M16C-109-0309)
When an external clock is input from the XIN pin and the main clock is used as the CPU clock, do not
stop the external clock.
28.5.4
Oscillator Stop/Restart Detect Function
•
In the following cases, set the CM20 bit to 0 (oscillator stop/restart detect function disabled), and
then change the setting of each bit.
- When the CM05 bit is set to 1 (main clock stopped)
- When the CM10 bit is set to 1 (stop mode)
•
To enter wait mode while using the oscillator stop/restart detect function, set the CM02 bit to 0
(peripheral function clock f1 not turned off during wait mode).
•
This function cannot be used if the main clock frequency is 2 MHz or lower. In that case, set the
CM20 bit to 0 (oscillator stop/restart detect function disabled).
•
While the CM27 bit is 1 (oscillation stop/restart detect interrupt), when the FRA01 bit is 1 (40 MHz
on-chip oscillator selected), set the FRA00 bit to 1 (40 MHz on-chip oscillator on). (Do not set the
FRA00 bit to 0 while FRA01 bit is 1, and vice versa.)
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
TAiOUT
Do not cross
XIN
VSS
XOUT
Bad
28. Usage Notes
Page 765 of 803
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