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M16C/5L Group, M16C/56 Group
6.4.4
Voltage Monitor 0 Reset
This reset is triggered by the MCU's on-chip voltage detector 0. The voltage detector 0 monitors the
voltage applied to the VCC pin (Vdet0).
The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC pin drops to Vdet0 or
below.
Then, the fOCO-S count starts when the voltage applied to the VCC pin rises to Vdet0 or above. The
internal reset signal becomes high after 128 cycles of fOCO-S, and then the MCU executes the
program at the address indicated by the reset vector. fOCO-S divided by 8 is automatically selected as
the CPU clock after reset.
The internal RAM is not reset. When the voltage applied to the VCC pin drops to Vdet0 or below while
writing data to the internal RAM, the internal RAM becomes undefined.
Refer to 7. "Voltage Detector" for details of the voltage monitor 0 reset.
6.4.5
Voltage Monitor 2 Reset
This reset is triggered by the MCU's on-chip voltage detector 2. Voltage detector 2 monitors the voltage
applied to the VCC pin (Vdet2).
When the VW2C6 bit in the VW2C register is 1 (voltage monitor 2 reset when Vdet2 passage is
detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC pin drops to
Vdet2 or below. fOCO-S divided by 8 is automatically selected as the CPU clock after reset.Then, after
the set amount of time, the MCU executes the program at the address indicated by the reset vector.
The LVD2R bit in the RSTFR register becomes 1 (voltage monitor 2 reset detected) after voltage
monitor 2 reset. Some SFRs are not reset at voltage monitor 2 reset. Refer to 4. "Special Function
Registers (SFRs)" for details.
The internal RAM is not reset.
Refer to 7. "Voltage Detector" for details of the voltage monitor 2 reset.
6.4.6
Oscillator Stop Detect Reset
The MCU resets and stops the pins, CPU, and SFRs when the CM27 bit in the CM2 register is 0 (reset
when oscillator stop detected), if it detects that the main clock oscillator has stopped.
The OSDR bit in the RSTFR register becomes 1 (oscillator stop detect reset detected) after oscillator
stop detect reset.
Some SFRs are not reset at oscillator stop detect reset. Refer to 4. "Special Function Registers (SFRs)"
for details. The internal RAM is not reset. When the main clock oscillator stop is detected while writing
data to the internal RAM, the internal RAM becomes undefined.
Oscillator stop detect reset is canceled by hardware reset or voltage monitor 0 reset.
Refer to 8.7 "Oscillator Stop/Restart Detect Function" for details.
6.4.7
Watchdog Timer Reset
The MCU resets the pins, CPU, and SFRs when the PM12 bit in the PM1 register is 1 (reset when
watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program
at the address determined by the reset vector. fOCO-S divided by 8 is automatically selected as the
CPU clock after reset.
The WDR bit in the RSTFR register becomes 1 (watchdog timer reset detected) after watchdog timer
reset. Some SFRs are not reset at watchdog timer reset. Refer to 4. "Special Function Registers
(SFRs)" for details.
The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal
RAM, the internal RAM becomes undefined.
Refer to 13. "Watchdog Timer" for details.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
6. Resets
Page 70 of 803
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