Renesas M16C/6NK Hardware Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Computer Hardware
  5. M16C/6NK
  6. Hardware manual

Renesas M16C/6NK Hardware Manual

16-bit single-chip microcomputer m16c family / m16c/60 series
Hide thumbs
1
2
3
4
Table Of Contents
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
Table of Contents

Advertisement

Quick Links

Download this manual
REJ09B0124-0200
16
Before using this material, please visit our website to verify that this is the most
updated document available.
Rev. 2.00
Revision date: Nov. 28, 2005
(M16C/6NK, M16C/6NM)
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C/6N Group
M16C FAMILY / M16C/60 SERIES
Hardware Manual
www.renesas.com

Advertisement

Table of Contents
loading

Related Manuals for Renesas M16C/6NK

Summary of Contents for Renesas M16C/6NK

  • Page 1 Before using this material, please visit our website to verify that this is the most updated document available. Rev. 2.00 Revision date: Nov. 28, 2005 (M16C/6NK, M16C/6NM) RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES M16C/6N Group Hardware Manual www.renesas.com...
  • Page 2 • The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

  • Page 3: How To Use This Manual

    How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below.
  • Page 4 Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTE: 1. Before using this material , please visit our website to verify that this is the most updated document available.

  • Page 5: Table Of Contents

    SFR Page Reference ... B-1 1. Overview ... 1 1.1 Applications ... 1 1.2 Performance Outline ... 2 1.3 Block Diagram ... 4 1.4 Product List ... 5 1.5 Pin Configuration ... 6 1.6 Pin Description ... 13 2. Central Processing Unit (CPU) ... 16 2.1 Data Registers (R0, R1, R2, and R3) ...
  • Page 6 7.2 Bus Control ... 46 7.2.1 Address Bus ... 46 7.2.2 Data Bus ... 46 7.2.3 Chip Select Signal ... 46 7.2.4 Read and Write Signals ... 48 7.2.5 ALE Signal ... 48 ________ 7.2.6 RDY Signal ... 49 7.2.8 BCLK Output ... 50 __________ 7.2.7 HOLD Signal ...
  • Page 7 10.5.4 Interrupt Sequence ... 89 10.5.5 Interrupt Response Time ... 90 10.5.6 Variation of IPL when Interrupt Request is Accepted ... 90 10.5.7 Saving Registers ... 91 10.5.8 Returning from an Interrupt Routine ... 92 10.5.9 Interrupt Priority ... 92 10.5.10 Interrupt Priority Resolution Circuit ...
  • Page 8 16. A/D Converter ... 202 16.1 Mode Description ... 206 16.1.1 One-shot Mode ... 206 16.1.2 Repeat Mode ... 208 16.1.3 Single Sweep Mode ... 210 16.1.4 Repeat Sweep Mode 0 ... 212 16.1.5 Repeat Sweep Mode 1 ... 214 16.2 Function ...
  • Page 9 20. Programmable I/O Ports ... 247 20.1 PDi Register ... 248 20.2 Pi Register, PC14 Register ... 248 20.3 PURj Register ... 248 20.4 PCR Register ... 248 21. Flash Memory Version ... 260 21.1 Memory Map ... 261 21.1.1 Boot Mode ... 262 21.2 Functions to Prevent Flash Memory from Rewriting ...
  • Page 10 23.9 DMAC ... 349 23.9.1 Write to DMAE Bit in DMiCON Register ... 349 23.10 Timers ... 350 23.10.1 Timer A ... 350 23.10.2 Timer B ... 354 23.11 Thee-Phase Motor Control Timer Function ... 356 23.12 Serial Interface ... 357 23.12.1 Clock Synchronous Serial I/O Mode ...

  • Page 11: Sfr Page Reference

    SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Chip Select Control Register 0009h Address Match Interrupt Enable Register 000Ah Protect Register 000Bh...
  • Page 12 Address Register 0080h 0081h 0082h CAN0 Message Box 2: Identifier / DLC 0083h 0084h 0085h 0086h 0087h 0088h 0089h CAN0 Message Box 2: Data Field 008Ah 008Bh 008Ch 008Dh 008Eh CAN0 Message Box 2: Time Stamp 008Fh 0090h 0091h 0092h CAN0 Message Box 3: Identifier / DLC 0093h 0094h...
  • Page 13 Address Register 0100h 0101h 0102h CAN0 Message Box 10: Identifier / DLC 0103h 0104h 0105h 0106h 0107h 0108h 0109h CAN0 Message Box 10: Data Field 010Ah 010Bh 010Ch 010Dh 010Eh CAN0 Message Box 10: Time Stamp 010Fh 0110h 0111h 0112h CAN0 Message Box 11: Identifier / DLC 0113h 0114h...
  • Page 14 Address Register 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h...
  • Page 15 Address Register 0200h CAN0 Message Control Register 0 0201h CAN0 Message Control Register 1 0202h CAN0 Message Control Register 2 0203h CAN0 Message Control Register 3 0204h CAN0 Message Control Register 4 0205h CAN0 Message Control Register 5 0206h CAN0 Message Control Register 6 0207h CAN0 Message Control Register 7 0208h...
  • Page 16 Address Register 0280h 0281h 0282h CAN1 Message Box 2: Identifier / DLC 0283h 0284h 0285h 0286h 0287h 0288h 0289h CAN1 Message Box 2: Data Field 028Ah 028Bh 028Ch 028Dh 028Eh CAN1 Message Box 2: Time Stamp 028Fh 0290h 0291h 0292h CAN1 Message Box 3: Identifier / DLC 0293h 0294h...
  • Page 17 Address Register 0300h 0301h 0302h CAN1 Message Box 10: Identifier / DLC 0303h 0304h 0305h 0306h 0307h 0308h 0309h CAN1 Message Box 10: Data Field 030Ah 030Bh 030Ch 030Dh 030Eh CAN1 Message Box 10: Time Stamp 030Fh 0310h 0311h 0312h CAN1 Message Box 11: Identifier / DLC 0313h 0314h...
  • Page 18 Address Register 0380h Count Start Flag 0381h Clock Prescaler Reset Flag 0382h One-Shot Start Flag 0383h Trigger Select Register 0384h Up/Down Flag 0385h 0386h Timer A0 Register 0387h 0388h Timer A1 Register 0389h 038Ah Timer A2 Register 038Bh 038Ch Timer A3 Register 038Dh 038Eh Timer A4 Register...

  • Page 19: Overview

    Being equipped with two CAN (Controller Area Network) modules in M16C/6N Group (M16C/6NK, M16C/6NM), the microcomputer is suited to car audio and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA and communication equipment which requires high-speed arithmetic/logic operations.

  • Page 20: Performance Outline

    This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NK, M16C/6NM). Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NK) Item...
  • Page 21 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) Item Number of Basic Instructions 91 instructions Minimum Instruction Execution Time Operation Mode...

  • Page 22: Block Diagram

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NK, M16C/6NM). Port P0 Internal peripheral functions Timer (16 bits)

  • Page 23: Product List

    This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NK, M16C/6NM) products and Figure 1.2 shows the type numbers, memory sizes and packages. Table 1.3 Product List Type No.

  • Page 24: Pin Configuration

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.5 Pin Configuration Figures 1.3 and 1.4 show the pin configuration (top view). Tables 1.4 to 1.8 list the pin characteristics. PIN CONFIGURATION (top view)
  • Page 25 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.4 Pin Characteristics for 100-Pin Package (1) Control Interrupt Pin No. Port P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN P8_7...
  • Page 26 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.5 Pin Characteristics for 100-Pin Package (2) Control Interrupt Pin No. Port P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1...
  • Page 27 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) PIN CONFIGURATION (top view) P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P11_7/SIN6 P11_6/SOUT6 P11_5/CLK6 P11_4 P11_3 P11_2/SOUT5 P11_1/SIN5 P11_0/CLK5 P10_7/AN7/KI3...
  • Page 28 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.6 Pin Characteristics for 128-Pin Package (1) Control Interrupt Pin No. Port VREF AVCC P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1...
  • Page 29 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.7 Pin Characteristics for 128-Pin Package (2) Control Interrupt Pin No. Port P5_6 P5_5 P5_4 P13_3 P13_2 P13_1 P13_0 P5_3 P5_2...
  • Page 30 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.8 Pin Characteristics for 128-Pin Package (3) Control Interrupt Pin No. Port P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2...

  • Page 31: Pin Description

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.6 Pin Description Tables 1.9 to 1.11 list the pin descriptions. Table 1.9 Pin Description (100-pin and 128-pin Versions) (1) Signal Name...
  • Page 32 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.10 Pin Description (100-pin and 128-pin Versions) (2) Signal Name Pin Name Main clock input Main clock XOUT output Sub clock...
  • Page 33 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 1.11 Pin Description (100-pin and 128-pin Versions) (3) Signal Name Pin Name I/O port P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7...

  • Page 34: Central Processing Unit (Cpu)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank.

  • Page 35: Frame Base Register (Fb)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

  • Page 36: Memory

    M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NK, M16C/6NM). The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.

  • Page 37: Special Function Register (Sfr)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.16 list the SFR information.
  • Page 38 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.2 SFR Information (2) Address 0040h 0041h CAN0/1 Wake-up Interrupt Control Register 0042h CAN0 Successful Reception Interrupt Control Register 0043h CAN0 Successful Transmission Interrupt Control Register...
  • Page 39 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h CAN0 Message Box 2: Identifier / DLC 0083h 0084h 0085h 0086h 0087h 0088h...
  • Page 40 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h CAN0 Message Box 6: Identifier / DLC 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h...
  • Page 41 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.5 SFR Information (5) Address 0100h 0101h 0102h CAN0 Message Box 10: Identifier / DLC 0103h 0104h 0105h 0106h 0107h 0108h...
  • Page 42 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.6 SFR Information (6) Address 0140h 0141h 0142h CAN0 Message Box 14: Identifier /DLC 0143h 0144h 0145h 0146h 0147h 0148h 0149h...
  • Page 43 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh...
  • Page 44 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.8 SFR Information (8) Address 01C0h Timer B3, B4, B5 Count Start Flag 01C1h 01C2h Timer A1-1 Register 01C3h 01C4h Timer A2-1 Register...
  • Page 45 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.9 SFR Information (9) Address 0200h CAN0 Message Control Register 0 CAN0 Message Control Register 1 0201h CAN0 Message Control Register 2...
  • Page 46 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.10 SFR Information (10) Address 0240h 0241h 0242h CAN0 Acceptance Filter Support Register 0243h 0244h CAN1 Acceptance Filter Support Register 0245h...
  • Page 47 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.11 SFR Information (11) Address 0280h 0281h 0282h CAN1 Message Box 2: Identifier / DLC 0283h 0284h 0285h 0286h 0287h 0288h...
  • Page 48 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.12 SFR Information (12) Address 02C0h 02C1h 02C2h CAN1 Message Box 6: Identifier / DLC 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h...
  • Page 49 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.13 SFR Information (13) Address 0300h 0301h 0302h CAN1 Message Box 10: Identifier / DLC 0303h 0304h 0305h 0306h 0307h 0308h...
  • Page 50 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.14 SFR Information (14) Address 0340h 0341h 0342h CAN1 Message Box 14: Identifier / DLC 0343h 0344h 0345h 0346h 0347h 0348h...
  • Page 51 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.15 SFR Information (15) Address 0380h Count Start Flag 0381h Clock Prescaler Reset Flag One-Shot Start Flag 0382h Trigger Select Register...
  • Page 52 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 4.16 SFR Information (16) Address 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h...

  • Page 53: Reset

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset The microcomputer resets pins, the CPU and SFR by setting the RESET pin.
  • Page 54 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) td(P-R) More than 20 cycles are needed RESET BCLK Microprocessor mode BYTE = H Address Microprocessor mode BYTE = L Address Single-chip...

  • Page 55: Software Reset

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5.2 Software Reset The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1”...

  • Page 56: Processor Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode Note 6. Processor Mode explains as an example of a Normal-ver.. T/V-ver. is available single-chip mode only. Not available memory expansion mode and microprocessor mode.

  • Page 57: Setting Processor Modes

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 6.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
  • Page 58 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Processor Mode Register 0 Bit symbol NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
  • Page 59 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Processor Mode Register 1 Bit symbol NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
  • Page 60 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Single-chip mode 00000h 00400h Internal RAM XXXXXh Can not use YYYYYh Internal ROM FFFFFh NOTES: 1. If the PM13 bit in the PM1 register is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
  • Page 61 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) When PM13 = 0 and PM10 = 0 Memory expansion mode 00000h 00400h Internal RAM XXXXXh Reserved area 04000h 08000h 27000h Reserved area...
  • Page 62 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) When PM13 = 0 and PM10 = 1 Memory expansion mode 00000h 00400h Internal RAM XXXXXh Reserved area 04000h 08000h Reserved area...

  • Page 63: Bus Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Bus Note 7. Bus explains as an example of a Normal-ver.. Not available the bus control pins in T/V-ver.. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/output to and from external devices.

  • Page 64: Bus Control

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 7.2.1 Address Bus The address bus consists of 20 lines, A0 to A19.
  • Page 65 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi.

  • Page 66: Read And Write Signals

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.2.4 Read and Write Signals When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD,...

  • Page 67: Rdy Signal

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) ________ 7.2.6 RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on...

  • Page 68: Bclk Output

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) __________ 7.2.7 HOLD Signal This signal is used to transfer control of the bus from CPU or DMAC to an external circuit. When the input...
  • Page 69 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 7.6 Pin Functions for Each Processor Mode Processor Mode Memory Expansion Mode or Microprocessor Mode PM05 to PM04 Bits 00b (separate bus)

  • Page 70: External Bus Status When Internal Area Accessed

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.2.9 External Bus Status When Internal Area Accessed Table 7.7 shows the external bus status when the internal area is accessed. Table 7.7 External Bus Status When Internal Area Accessed...
  • Page 71 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 7.8 Software Wait Related Bits and Bus Cycles PM2 Register PM1 Register Area Bus Mode PM20 Bit PM17 Bit Internal ROM, RAM...
  • Page 72 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) Separate bus, No wait setting BCLK Write signal Read signal Data bus Address bus (2) Separate bus, 1-wait setting BCLK Write signal...
  • Page 73 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) Separate bus, 3-wait setting BCLK Write signal Read signal Data bus Address bus (2)Multiplexed bus, 1- or 2-wait setting BCLK Write signal...

  • Page 74: Clock Generating Circuit

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8. Clock Generating Circuit 8.1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal: • Main clock oscillation circuit •...
  • Page 75 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Sub clock oscillation circuit XCIN CM04 CM10=1 (stop mode) Main clock CM05 oscillation circuit WAIT instruction RESET Software reset Interrupt request level...
  • Page 76 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) System Clock Control Register 0 Bit Symbol NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
  • Page 77 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) System Clock Control Register 1 Bit Symbol NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable) 2.
  • Page 78 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Oscillation Stop Detection Register Bit Symbol NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
  • Page 79 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Peripheral Clock Select Register Bit Symbol NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
  • Page 80 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CAN0/1 Clock Select Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
  • Page 81 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) PLL Control Register 0 Bit Symbol NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).

  • Page 82: Main Clock

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) The following describes the clocks generated by the clock generating circuit. 8.1.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.

  • Page 83: Sub Clock

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources.

  • Page 84: On-Chip Oscillator Clock

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks.
  • Page 85 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Using the PLL clock as the clock source for the CPU Set the CM07 bit to "0" (main clock), the CM17 to CM16 bits to "00b"...

  • Page 86: Cpu Clock And Peripheral Function Clock

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.

  • Page 87: Power Control

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document.
  • Page 88 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks.

  • Page 89: Wait Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer.
  • Page 90 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 8.5 Interrupts to Exit Wait Mode and Use Conditions Interrupt _______ NMI Interrupt Can be used Serial Interface Interrupt Can be used when operating with...

  • Page 91: Stop Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
  • Page 92 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.4.3.3 Exiting Stop Mode Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. When the hardware reset or NMI interrupt is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to “000b”...
  • Page 93 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Figure 8.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure 8.13 shows the state transition in normal operation mode.
  • Page 94 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Main Clock Oscillation PLL operation mode High-Speed Mode PLC07 = 1 CPU clock CPU clock CM11 = 1 : f(PLL) : f(XIN)
  • Page 95 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 8.8 Allowed Transition and Setting High-Speed Mode, Low-Speed Low Power PLL Operation On-chip Oscillator On-chip Oscillator Medium-Speed Mode High-Speed Mode, (NOTE 8)

  • Page 96: Oscillation Stop And Re-Oscillation Detection Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected.

  • Page 97: How To Use Oscillation Stop And Re-Oscillation Detection Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt.

  • Page 98: Protection

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily.

  • Page 99: Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10. Interrupt 10.1 Type of Interrupts Figure 10.1 shows the types of interrupts. Software (Non-maskable interrupt) Interrupt Hardware NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.

  • Page 100: Software Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 10.2.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction.

  • Page 101: Hardware Interrupts

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 10.3.1 Special Interrupts Special interrupts are non-maskable interrupts.

  • Page 102: Interrupts And Interrupt Vector

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors.
  • Page 103 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 10.2 Relocatable Vector Tables Interrupt Source BRK Instruction (10) CAN0/1 Wake-up CAN0 Successful Reception CAN0 Successful Transmission ________ INT3 (12) Timer B5, SI/O5...

  • Page 104: Interrupt Control

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts.
  • Page 105 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Interrupt Control Register Bit Symbol NOTES: 1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register.

  • Page 106: I Flag

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.

  • Page 107: Interrupt Sequence

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed —...

  • Page 108: Interrupt Response Time

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5.5 Interrupt Response Time Figure 10.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.

  • Page 109: Saving Registers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.

  • Page 110: Returning From An Interrupt Routine

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
  • Page 111 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Priority level of each interrupt INT1 Timer B2 Timer B0, SI/O6 Timer A3, INT6 Timer A1 UART1 Reception, ACK1 UART0 Reception, ACK0...

  • Page 112: Int Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) ______ 10.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register.
  • Page 113 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Interrupt Request Cause Select Register 0 Bit Symbol IFSR00 IFSR01 IFSR02 IFSR03 IFSR04 IFSR05 IFSR06 IFSR07 NOTES: 1.When the IFSR16 bit in the IFSR1 register = 0, CAN1 successful transmission and SI/O3 share the vector and interrupt control register.
  • Page 114 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Interrupt Request Cause Select Register 1 Bit Symbol IFSR10 IFSR11 IFSR12 IFSR13 IFSR14 IFSR15 IFSR16 IFSR17 NOTES: 1.When setting this bit to "1" (both edges), make sure the POL bit in the INT0IC to INT5IC register is set to "0"...
  • Page 115 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Interrupt Request Cause Select Register 2 Bit Symbol IFSR20 IFSR21 IFSR22 IFSR23 IFSR24 IFSR25 IFSR26 NOTES: 1.When setting this bit to "1" (both edges), make sure the POL bit in the INT6IC to INT8IC registers are set to "0"...

  • Page 116: Nmi Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) ______ 10.7 NMI Interrupt _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt.

  • Page 117: Address Match Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register.
  • Page 118 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Address Match Interrupt Enable Register Address Match Interrupt Enable Register 2 Address Match Interrupt Register i (i = 0 to 3) (b23)

  • Page 119: Watchdog Timer

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.

  • Page 120: Count Source Protective Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Watchdog Timer Control Register Bit Symbol Watchdog Timer Start Register The watchdog timer is initialized and starts counting after a write instruction to this register.

  • Page 121: Dmac

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from the source address to the destination address.
  • Page 122 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 12.1 DMAC Specifications Item No. of Channels Transfer Memory Space Maximum No. of Bytes Transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
  • Page 123 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) DMA0 Request Cause Select Register Bit Symbol NOTE: 1. The causes of DMA0 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits in the manner described below.
  • Page 124 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) DMA1 Request Cause Select Register NOTE: 1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits in the manner described below.
  • Page 125 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) DMAi Source Pointer (i = 0, 1) (b23) (b19) (b16) (b15) b0 b7 NOTE: 1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the DMiCON register is "0"...

  • Page 126: Transfer Cycle

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle.
  • Page 127 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address CPU use...

  • Page 128: Dma Transfer Cycles

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 12.2 shows the number of DMA transfer cycles. Table 12.3 shows the coefficient j, k.

  • Page 129: Dma Enable

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the...

  • Page 130: Channel Priority And Dma Transfer Timing

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1”...

  • Page 131: Timers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc.
  • Page 132 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Main clock PLL clock On-chip oscillator clock f1 or f2 f8 f32 fC32 TCK1 to TCK0 TB0IN TCK1 to TCK0 TB1IN TCK1 to TCK0...

  • Page 133: Timer A

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1 Timer A Figure 13.3 shows a block diagram of the timer A. Figures 13.4 to 13.6 show the timer A-related registers.
  • Page 134 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 0 to 4) Bit Symbol Timer Ai Register (i = 0 to 4) (b15) (b8) b0 b7...
  • Page 135 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Count Start Flag Bit Symbol Up/Down Flag Bit Symbol NOTES: 1.Use the MOV instruction to write to this register. 2.Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to "0"...
  • Page 136 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) One-Shot Start Flag NOTES: 1.Make sure the PD7_1 bit in the PD7 register is set to "0" (input mode). 2.Over flow or under flow.

  • Page 137: Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.1 lists specifications in timer mode. Figure 13.7 shows TAiMR register in timer mode.

  • Page 138: Event Counter Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 13.2 lists specifications in event counter mode (when not processing two-phase pulse signal).
  • Page 139 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 0 to 4) (When not using two-phase pulse signal processing) Bit Symbol TMOD0 TMOD1 NOTES: 1.During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
  • Page 140 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 13.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins Count Operation •...
  • Page 141 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 2 to 4) (When using two-phase pulse signal processing) Bit Symbol TMOD0 TMOD1 NOTES: 1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in normal processing mode and x4 processing mode, respectively.
  • Page 142 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing.

  • Page 143: One-Shot Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period.
  • Page 144 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 0 to 4) Bit Symbol TMOD0 TMOD1 TCK0 TCK1 NOTES: 1.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).

  • Page 145: Pulse Width Modulation (Pwm) Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator.
  • Page 146 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 0 to 4) Bit Symbol TMOD0 TMOD1 TCK0 TCK1 NOTES: 1.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).
  • Page 147 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Count source "H" Input signal to TAiIN pin "L" "H" PWM pulse output from TAiOUT pin "L" IR bit in TAiIC "1"...

  • Page 148: Timer B

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.2 Timer B Figure 13.15 shows a block diagram of the timer B. Figures 13.16 and 13.17 show the timer B-related registers.
  • Page 149 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Bi Mode Register (i = 0 to 5) Bit Symbol TMOD0 TMOD1 TCK0 TCK1 NOTES: 1. Timer B0, timer B3. 2. Timer B1, timer B2, timer B4, timer B5.
  • Page 150 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Count Start Flag Bit Symbol Timer B3, B4, B5 Count Start Flag Bit Symbol Clock Prescaler Reset Flag Bit Symbol Figure 13.17 TABSR Register, TBSR Register and CPSRF Register Rev.2.00...

  • Page 151: Timer Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.2.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.6 lists specifications in timer mode. Figure 13.18 shows TBiMR register in timer mode.

  • Page 152: Event Counter Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 13.7 lists specifications in event counter mode. Figure 13.19 shows TBiMR register in event counter mode.

  • Page 153: Pulse Period And Pulse Width Measurement Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal.
  • Page 154 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Bi Mode Register (i = 0 to 5) TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 TCK0 TCK1 NOTE: 1.
  • Page 155 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Count source "H" Measurement pulse "L" Reload register counter transfer timing Timing at which counter reaches "0000h" "1" TBiS bit "0" "1"...

  • Page 156: Three-Phase Motor Control Timer Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Three-Phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 14.1 lists the specifications of the three-phase motor control timer function.
  • Page 157 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) INV00 to INV07: Bits in INVC0 register INV10 to INV15: Bits in INVC1 register DUi, DUBi: Bits in IDBi register (i = 0, 1)
  • Page 158 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Three-Phase PWM Control Register 0 NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
  • Page 159 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Three-Phase PWM Control Register 1 Symbol INV16 NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
  • Page 160 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Three-Phase Output Buffer Register i (i = 0, 1) NOTE: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger.
  • Page 161 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai, Ai-1 Register (i = 1, 2, 4) TA1, TA2, TA4 TA11, TA21, TA41 If setting value is n, the timer stops when the nth count source is counted after a start trigger is generated.
  • Page 162 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer B2 Interrupt Occurrence Frequency Set Counter NOTES: 1. Use the MOV instruction to set the ICTB2 register. 2. If the INV01 bit is set to "1", set the ICTB2 register when the TB2S bit is set to "0" (timer B2 counter stopped), If the INV01 bit is set to "0"...
  • Page 163 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Trigger Select Register TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH NOTES: 1. Set the corresponding port direction bit to "0" (input mode).
  • Page 164 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timer Ai Mode Register (i = 1, 2, 4) Timer B2 Mode Register Figure 14.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register Rev.2.00...
  • Page 165 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
  • Page 166 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start Trigger Signal Timer A4 One-Shot Pulse U-Phase Output...

  • Page 167: Serial Interface

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. Serial Interface Serial interface is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 NOTE: 1. 100-pin version supports 5 channels; UART0 to UART2, SI/O3, SI/O4 128-pin version supports 7 channels;...
  • Page 168 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Main clock, PLL clock, or on-chip oscillator clock (UART0) RXD polarity RXD0 reversing circuit Clock source selection CLK1 to CLK0 CKDIR Internal...
  • Page 169 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Main clock, PLL clock, or on-chip oscillator clock (UART2) RXD polarity reversing RXD2 circuit Clock source selection CLK1 to CLK0 CKDIR Internal...
  • Page 170 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) IOPOL No reverse RXDi RXD data reverse circuit Reverse PRYE STPS enabled PRYE STPS enabled disabled i = 0 to 2 SP: Stop bit...
  • Page 171 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UARTi Transmit Buffer Register (i = 0 to 2) (b15) (b8) NOTE: 1. Use the MOV instruction to write to this register.
  • Page 172 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UARTi Transmit/Receive Mode Register (i = 0 to 2) NOTES: 1. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
  • Page 173 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UARTj Transmit/Receive Control Register 1 (j = 0, 1) NOTE: 1. The UjLCH bit is enabled when the SMD2 to SMD0 bits in the UjMR register are set to "001b" (clock synchronous serial I/O mode), "100b"...
  • Page 174 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UART Transmit/Receive Control Register 2 CLKMD0 CLKMD1 NOTE: 1. When using multiple transfer clock output pins, make sure the following conditions are met:...
  • Page 175 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UARTi Special Mode Register 2 (i = 0 to 2) UARTi Special Mode Register 3 (i = 0 to 2) NOTES: 1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I In other than I C mode, set these bits to "000b"...
  • Page 176 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) UARTi Special Mode Register 4 (i = 0 to 2) STAREQ RSTAREQ STPREQ STSPSEL NOTE: 1. Set to "0" when each condition is generated.

  • Page 177: Clock Synchronous Serial I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 15.1 lists the specifications of the clock synchronous serial I/O mode.
  • Page 178 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register UiTB 0 to 7 UiRB 0 to 7...
  • Page 179 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 15.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected.
  • Page 180 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) Example of Transmit Timing (when internal clock is selected) Transfer clock "1" TE bit in UiC1 register "0" Write data to the UiTB register "1"...
  • Page 181 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
  • Page 182 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
  • Page 183 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted.
  • Page 184 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) _______ _______ 15.1.1.7 CTS/RTS Function _______ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi (i = 0 to 2) pin.

  • Page 185: Clock Asynchronous Serial I/O (Uart) Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format.
  • Page 186 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.6 Registers to Be Used and Settings in UART Mode Register UiTB 0 to 8 UiRB 0 to 8 OER,FER,PER,SUM Error flag...
  • Page 187 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.7 lists the functions of the input/output pins during UART mode. Table 15.8 lists the P6_4 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an “H”.
  • Page 188 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit) Transfer clock "1" TE bit in UiC1 register "0"...
  • Page 189 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) • Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit) UiBRG count source "1" RE bit in UiC1 register "0"...
  • Page 190 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
  • Page 191 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register.
  • Page 192 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) _______ _______ 15.1.2.6 CTS/RTS Function _______ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i = 0 to 2) pin.

  • Page 193: Special Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.3 Special Mode 1 (I C mode is provided for use as a simplified I of the I C mode. Figure 15.23 shows the block diagram for I in the I C mode and the register values set.
  • Page 194 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) SDAi STSPSEL=1 Delay circuit STSPSEL=0 ACKC=1 ACKC=0 ACKD bit Noise Filter Start condition detection Stop condition detection Falling edge detection SCLi IICM=0...
  • Page 195 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.11 Registers to Be Used and Settings in I Register UiTB 0 to 7 UiRB 0 to 7 UiBRG 0 to 7...
  • Page 196 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.12 I C Mode Functions Clock Synchronous Serial I/O Mode Function (SMD2 to SMD0 = 001b, IICM = 0) Factor of Interrupt...
  • Page 197 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit SCLi SDAi (2) IICM2 = 0, CKPH = 1 (clock delay)
  • Page 198 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
  • Page 199 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.13 STSPSEL Bit Functions Function Output of SCLi and SDAi Pins Start/Stop Condition Interrupt Request Generation Timing (1) When slave CKDIR bit = 1 (external clock)
  • Page 200 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 15.24. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
  • Page 201 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to “1”...

  • Page 202: Special Mode 2

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 15.14 lists the specifications of Special Mode 2. Figure 15.27 shows communication control example for Special Mode 2.
  • Page 203 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Microcomputer Figure 15.27 Serial Bus Communication Control Example (UART2) Rev.2.00 Nov 28, 2005 page 185 of 378 REJ09B0124-0200 P1_3 P1_2 P7_2(CLK2) P7_1(RXD2)
  • Page 204 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.15 Registers to Be Used and Settings in Special Mode 2 Register UiTB 0 to 7 UiRB 0 to 7 UiBRG...
  • Page 205 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register.
  • Page 206 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) "H" Slave control input "L" "H" Clock input "L" (CKPOL= 0, CKPH = 0) Clock input "H" (CKPOL = 1, CKPH = 0) "L"...

  • Page 207: Special Mode 3 (Ie Mode)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
  • Page 208 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) ABSCS Bit in UiSMR Register (bus collision detect sampling clock select) If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock...

  • Page 209: Special Mode 4 (Sim Mode) (Uart2)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
  • Page 210 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.18 Registers to Be Used and Settings in SIM Mode Register U2TB 0 to 7 U2RB 0 to 7 OER,FER,PER,SUM Error flag...
  • Page 211 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) (1) Transmission Transfer clock "1" TE bit in U2C1 register "0" "1" TI bit in U2C1 register "0" Start TXD2 Parity error signal sent...
  • Page 212 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Figure 15.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer Figure 15.33 SIM Interface Connection 15.1.6.1 Parity Error Signal Output...
  • Page 213 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.1.6.2 Format When direct format, set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0”...

  • Page 214: Si/Oi

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.2 SI/Oi (i = 3 to 6) SI/Oi is exclusive clock-synchronous serial I/Os. Figure 15.36 shows the block diagram of SI/Oi, and Figures 15.37 and 15.38 show the SI/Oi-related registers.Table 15.19 lists the specifications of SI/Oi.
  • Page 215 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) SI/Oi Control Register (i = 3 to 6) b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to "1"...
  • Page 216 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) SI/O3, 4, 5, 6 Transmit/Receive Register Bit Symbol NOTES: 1. The S3TRF to S6TRF bits can only be reset by writing to "0".
  • Page 217 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 15.19 SI/Oi Specifications Item Transfer Data Format Transfer data length: 8 bits Transfer clock • SMi6 bit in SiC register = 1 (internal clock) : fj/2(n+1) fj = f1SIO, f8SIO, f32SIO.

  • Page 218: Si/Oi Operation Timing

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.2.1 SI/Oi Operation Timing Figure 15.39 shows the SI/Oi operation timing. 1.5 cycle (max.) "H" SI/Oi internal clock "L" "H" CLKi output "L"...

  • Page 219: Functions For Setting An Souti Initial Value

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring Figure 15.41 shows the timing chart for setting an SOUTi initial value and how to set it.

  • Page 220: A/D Converter

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, P0_0 to P0_7, and P2_0 to P2_7.
  • Page 221 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Software trigger ADTRG VCUT VREF Resistor ladder AVSS Successive conversion register Data bus high-order Data bus low-order PM00 PM01 Port P0 group...
  • Page 222 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
  • Page 223 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 2 Bit Symbol ADGSEL0 ADGSEL1 NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 224: Mode Description

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.1 Mode Description 16.1.1 One-shot Mode In one-shot mode, analog voltage applied to a selected pin is A/D converted once. Table 16.2 lists the specifications of one-shot mode.
  • Page 225 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 226: Repeat Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 16.3 lists the specifications of repeat mode. Figure 16.5 shows the ADCON0 and ADCON1 registers in repeat mode.
  • Page 227 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 228: Single Sweep Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code.
  • Page 229 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 230: Repeat Sweep Mode 0

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
  • Page 231 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 232: Repeat Sweep Mode 1

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code.
  • Page 233 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) A/D Control Register 0 Bit Symbol NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

  • Page 234: Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.2 Function 16.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1”...

  • Page 235: Current Consumption Reducing Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register.
  • Page 236 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Sensor equivalent circuit Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit Rev.2.00 Nov 28, 2005 page 218 of 378 REJ09B0124-0200 Microcomputer R (7.8 kΩ)

  • Page 237: D/A Converter

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 17. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the DAiE bit in the DACON register to “1”...
  • Page 238 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) D/A Control Register Bit Symbol NOTE: 1. When not using the D/A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary current consumption in the chip and set the DAi register to "00h"...

  • Page 239: Crc Calculation

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC-CCITT (X The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit unit.
  • Page 240 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Setup procedure and CRC operation when generating CRC code "80C4h" CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is...

  • Page 241: Can Module

    M16C/6N Group (M16C/6NK, M16C/6NM) 19. CAN Module The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers is a communication controller implementing the CAN 2.0B protocol. The M16C/6N Group (M16C/6NK, M16C/6NM) contains two CAN modules which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats.

  • Page 242: Can Module-Related Registers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.1 CAN Module-Related Registers The CANi (i = 0, 1) module has the following registers. 19.1.1 CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.

  • Page 243: Cani Message Box

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.2 CANi Message Box (i = 0, 1) Table 19.1 shows the memory mapping of the CANi message box. It is possible to access to the message box in byte or word.
  • Page 244 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Figures 19.2 and 19.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed.

  • Page 245: Acceptance Mask Registers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.3 Acceptance Mask Registers Figures 19.4 and 19.5 show the CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR register, in which bit mapping in byte access and word access are shown.

  • Page 246: Can Sfr Registers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.4 CAN SFR Registers Figures 19.6 to 19.11 show the CAN SFR registers. CANi Message Control Register j (i = 0, 1) ( j = 0 to 15) NOTES: 1.
  • Page 247 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CANi Control Register (i = 0, 1) NOTES: 1. When the Reset bit is set to "1" (CAN "1" (Reset mode). 2. Change this bit only in the CAN reset/initialization mode.
  • Page 248 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CANi Status Register (i = 0, 1) NOTE: 1. These bits can be changed only when a slot which an interrupt is enabled by the CiICR register is transmitted or received successfully.
  • Page 249 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CANi Slot Status Register (i = 0, 1) (b15) (b8) b0 b7 CANi Interrupt Control Register (i = 0, 1) (b15) (b8)
  • Page 250 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CANi Configuration Register (i = 0, 1) NOTE: 1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bit (i = 0 to 2, 4 to 6) in the CCLKR register.
  • Page 251 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) CANi Receive Error Count Register (i = 0, 1) NOTE: 1. The value is indeterminate in bus off state. CANi Transmit Error Count Register (i = 0, 1) NOTE: 1.

  • Page 252: Operational Modes

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.5 Operational Modes The CAN module has the following four operational modes. • CAN Reset/Initialization Mode • CAN Operation Mode • CAN Sleep Mode •...

  • Page 253: Can Operation Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to “0”. If the Reset bit is set to “0”, check that the State_Reset bit in the CiSTR register is set to “0”.

  • Page 254: Bus Off State

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to the CAN operation mode from the bus off state, the module has the following two cases.

  • Page 255: Configuration Can Module System Clock

    M16C/6N Group (M16C/6NK, M16C/6NM) 19.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NK, M16C/6NM) has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the CiCONR register (i = 0, 1).

  • Page 256: Bit-Rate

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.8 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit.

  • Page 257: Acceptance Filtering Function And Masking Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.9 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR register can perform masking to the standard ID and the extended ID of 29 bits.

  • Page 258: Acceptance Filter Support Unit (Asu)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.10 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search.

  • Page 259: Basic Can Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register (i = 0, 1) is set to “1” (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode.

  • Page 260: Return From Bus Off Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.12 Return from Bus Off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to “1”...

  • Page 261: Reception And Transmission

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.15 Reception and Transmission Table 19.3 shows configuration of CAN reception and transmission mode. Table 19.3 Configuration of CAN Reception and Transmission Mode...

  • Page 262: Reception

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.15.1 Reception Figure 19.20 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj register (i = 0, 1, j = 0 to 15) and leads to losing/overwriting of the first message.

  • Page 263: Transmission

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.15.2 Transmission Figure 19.21 shows the timing of the transmit sequence. TrmReq bit TrmActive bit SentData bit CANi Successful Transmission Interrupt TrmState bit...

  • Page 264: Can Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.16 CAN Interrupt The CAN module provides the following CAN interrupts. • CANi Successful Reception Interrupt ( i = 0, 1) • CANi Successful Transmission Interrupt •...

  • Page 265: Programmable I/O Ports

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 in the 100-pin version and consist of 113 lines P0 to P14 in the 128-pin version.

  • Page 266: Pdi Register

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure20.7 shows the PDi register.
  • Page 267 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Figure20.1 I/O Ports (1) Rev.2.00 Nov 28, 2005 page 249 of 378 REJ09B0124-0200 Pull-up selection Direction register Port P1 control register Port latch...
  • Page 268 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Figure20.2 I/O Ports (2) Rev.2.00 Nov 28, 2005 page 250 of 378 REJ09B0124-0200 Pull-up selection Direction register "1" Output Port latch Data bus...
  • Page 269 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Data bus Input to respective peripheral functions Data bus Data bus Data bus Input to respective peripheral functions Figure20.3 I/O Ports (3) Rev.2.00...
  • Page 270 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) P10_0 to P10_3 P10_4 to P10_7 P9_3, P9_4 P9_6 P9_5 Figure20.4 I/O Ports (4) Rev.2.00 Nov 28, 2005 page 252 of 378...
  • Page 271 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) P8_7 Data bus P8_6 Data bus NOTE: Figure20.5 I/O Ports (5) BYTE BYTE signal input CNVSS CNVSS signal input RESET RESET signal input NOTE: Symbolizes a parasitic diode.
  • Page 272 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Port Pi Direction Register (i = 0 to 7, 9 to 13) Bit Symbol NOTES: 1. Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRC2 bit in the PRCR register to "1"...
  • Page 273 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Port Pi Register (i = 0 to 7, 9 to 13) NOTES: 1. Since P7_1 and P9_1 are N channel open-drain ports, the data is high-impedance.
  • Page 274 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Pull-up Control Register 0 NOTES: 1. During memory expansion and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified.
  • Page 275 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Pull-up Control Register 3 (128-pin version) Bit Symbol NOTES: 1. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
  • Page 276 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 20.2 Unassigned Pin Handling in Single-chip Mode Pin Name Ports P0 to P7, P8_0 to P8_4, P8_6, P8_7, P9 to P14...
  • Page 277 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Microcomputer Port P0 to P14 (Input mode) (except for P8_5) (Input mode) (Output mode) Open XOUT AVCC BYTE AVSS VREF In single-chip mode NOTES: 1.If the PM07 bit in the PM0 register is set to "1"...

  • Page 278: Flash Memory Version

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version.

  • Page 279: Memory Map

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.1 Memory Map The flash memory contains the user ROM area and a boot ROM area. The user ROM area has space to store the microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space as the block A.

  • Page 280: Boot Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “H ” signal is applied to the CNVSS and P5_0 pins and an “L ”...
  • Page 281 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) ROM Code Protect Control Address NOTES: 1. The ROMCP address is set to "FFh" when a block, including the ROMCP address, is erased.

  • Page 282: Cpu Rewrite Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer is mounted on a board without using a parallel, serial or CAN programmer.

  • Page 283: Ew0 Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”.

  • Page 284: Fmr0, Fmr1 Registers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.3 FMR0, FMR1 Registers Figure 21.4 shows FMR0 and FMR1 registers. Flash Memory Control Register 0 Bit Symbol NOTES: 1.This status includes writing or reading with the lock bit program or read lock bit status command.
  • Page 285 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.3.1 FMR00 Bit This bit indicates the flash memory operating status. It is set to “0” while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed;...
  • Page 286 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.3.7 FMR07 Bit This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to “1” when an erase error occurs;...
  • Page 287 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Procedure to enter EW0 mode Single-chip mode, memory expansion mode or boot mode Transfer the rewrite control program in CPU rewrite mode to a space other than the flash memory...
  • Page 288 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Transfer a low power dissipation mode or on-chip oscillator low power dissipation mode program to a space other the flash memory Jump to the low power dissipation mode or on-chip...

  • Page 289: Precautions On Cpu Rewrite Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.4 Precautions on CPU Rewrite Mode 21.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode).
  • Page 290 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 21.3.4.10 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to “0” (CPU rewrite mode disabled) before executing the WAIT instruction.

  • Page 291: Software Commands

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8 bits (D15 to D8) are ignored.
  • Page 292 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start.
  • Page 293 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.5.5 Block Erase Command The block erase command erases each block. By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) will start in the specified block.
  • Page 294 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify) operation will run continuously in all blocks except the block A.
  • Page 295 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block.

  • Page 296: Data Protect Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit in the FMR0 register to “0”...
  • Page 297 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 21.5 Status Register Bits in Status Bits in FMR0 Status Name Register Register SR0 (D0) Reserved SR1 (D1) Reserved SR2 (D2)

  • Page 298: Full Status Check

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.3.8 Full Status Check If an error occurs when a program or erase operation is completed, the FMR06, FMR07 bits in the FMR0 register are set to “1”, indicating a specific error.
  • Page 299 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Full status check FMR06 =1 FMR07=1? FMR07=0? FMR06=0? Full status check completed FMR06, FMR07: Bits in FMR0 register NOTE: 1. When either FMR06 or FMR07 bit is set to "1" (terminated by error), the program, block erase, erase all unlocked block, lock bit program and read lock bit status commands cannot be accepted.

  • Page 300: Standard Serial I/O Mode

    M16C/6N Group (M16C/6NK, M16C/6NM) 21.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer.
  • Page 301 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 21.7 Pin Functions for Standard Serial I/O Mode Name VCC1, VCC2, VSS Power supply input CNVSS CNVSS _____________ RESET Reset input...
  • Page 302 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) M16C/6N Group (M16C/6NK) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Figure 21.13 Pin Connections for Standard Serial I/O Mode (1)
  • Page 303 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) M16C/6N Group (M16C/6NM) (Flash memory version) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Figure 21.14 Pin Connections for Standard Serial I/O Mode (2)

  • Page 304: Example Of Circuit Application In Standard Serial I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 21.15 and 21.16 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively.

  • Page 305: Parallel I/O Mode

    In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM). Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.

  • Page 306: Can I/O Mode

    M16C/6N Group (M16C/6NK, M16C/6NM) 21.6 CAN I/O Mode In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the CAN programmer, contact your CAN programmer manufacturer.
  • Page 307 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) M16C/6N Group (M16C/6NK) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Figure 21.17 Pin Connections for CAN I/O Mode (1)
  • Page 308 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) M16C/6N Group (M16C/6NM) (Flash memory version) 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Figure 21.18 Pin Connections for CAN I/O Mode (2)

  • Page 309: Example Of Circuit Application In Can I/O Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.6.2 Example of Circuit Application in CAN I/O Mode Figure 21.19 shows example of circuit application in CAN I/O mode. Refer to the user’s manual of your CAN programmer to handle pins controlled by a CAN programmer.

  • Page 310: Electrical Characteristics

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Electrical Characteristics 22.1 Electrical Characteristics (Normal-ver.) Table 22.1 Absolute Maximum Ratings Symbol Parameter Supply Voltage (VCC1 = VCC2) Analog Supply Voltage...
  • Page 311 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.2 Recommended Operating Conditions (1) Symbol Supply Voltage (VCC1 = VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input...
  • Page 312 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.3 Recommended Operating Conditions (2) Symbol f(XIN) Main Clock Input Oscillation No Wait Mask ROM Version VCC = 3.0 to 5.5V...
  • Page 313 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.4 Electrical Characteristics (1) Symbol Parameter HIGH Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,...
  • Page 314 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.5 Electrical Characteristics (2) Symbol Parameter Power Supply Output pins are open Current and other pins are VSS. (VCC = 3.0 to 5.5V) NOTES: 1.
  • Page 315 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.6 A/D Conversion Characteristics Symbol Parameter – Resolution Integral 10 bits Nonlinearity Error 8 bits – Absolute 10 bits Accuracy 8 bits Differential Nonlinearity Error –...
  • Page 316 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.8 Flash Memory Version Electrical Characteristics Symbol Program and Erase Endurance Word Program Time (VCC = 5.0V) Lock Bit Program Time Block Erase Time (VCC = 5.0V)
  • Page 317 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.11 External Clock Input (XIN Input)
  • Page 318 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.13 Timer A Input (Counter Input in Event Counter Mode)
  • Page 319 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.19 Timer B Input (Counter Input in Event Counter Mode)
  • Page 320 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 5V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.25 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
  • Page 321 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 5V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.26 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
  • Page 322 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 5V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.27 Memory Expansion Mode and Microprocessor Mode...
  • Page 323 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) XIN input TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected)
  • Page 324 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH...

  • Page 325: Read Timing

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK d(BCLK-CS) 25ns.max tcyc d(BCLK-AD) 25ns.max d(BCLK-ALE) 25ns.max d(BCLK-RD) ac1(RD-DB) (0.5 ✕...
  • Page 326 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK d(BCLK-CS) 25ns.max tcyc d(BCLK-AD) 25ns.max d(BCLK-ALE) 25ns.max...
  • Page 327 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK d(BCLK-CS) 25ns.max d(BCLK-AD) 25ns.max d(BCLK-ALE) h(BCLK-ALE) 25ns.max...
  • Page 328 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK d(BCLK-CS) 25ns.max d(BCLK-AD) 25ns.max d(BCLK-ALE) h(BCLK-ALE) 25ns.max...
  • Page 329 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK d(BCLK-CS) 25ns.max...
  • Page 330 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK d(BCLK-CS) 25ns.max d(AD-ALE) (0.5 ✕...
  • Page 331 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.28 Electrical Characteristics Symbol Parameter HIGH Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,...
  • Page 332 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 3.3V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.29 External Clock Input (XIN Input)
  • Page 333 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 3.3V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.31 Timer A Input (Counter Input in Event Counter Mode)
  • Page 334 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 3.3V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.37 Timer B Input (Counter Input in Event Counter Mode)
  • Page 335 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 3.3V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.43 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
  • Page 336 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 3.3V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.44 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
  • Page 337 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Switching Characteristics (Referenced to VCC = 3.3V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified) Table 22.45 Memory Expansion Mode and Microprocessor Mode...
  • Page 338 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) XIN input TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected)
  • Page 339 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) BCLK (Separate bus) WR, WRL, WRH (Separate bus) (Multiplexed bus) WR, WRL, WRH...
  • Page 340 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK d(BCLK-CS) 30ns.max tcyc d(BCLK-AD) 30ns.max d(BCLK-ALE) 30ns.max d(BCLK-RD) ac1(RD-DB) (0.5 ✕...
  • Page 341 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK d(BCLK-CS) 30ns.max tcyc d(BCLK-AD) 30ns.max d(BCLK-ALE) 30ns.max...
  • Page 342 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc BCLK d(BCLK-CS) 30ns.max d(BCLK-AD) 30ns.max d(BCLK-ALE) h(BCLK-ALE) 30ns.max...
  • Page 343 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc BCLK d(BCLK-CS) 30ns.max d(BCLK-AD) 30ns.max d(BCLK-ALE) h(BCLK-ALE) 30ns.max...
  • Page 344 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK d(BCLK-CS) 40ns.max d(AD-ALE) (0.5 ✕...
  • Page 345 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc BCLK d(BCLK-CS) 40ns.max d(AD-ALE) (0.5 ✕...

  • Page 346: Electrical Characteristics (T/V-Ver.)

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22.2 Electrical Characteristics (T/V-ver.) Table 22.46 Absolute Maximum Ratings Symbol Parameter Supply Voltage (VCC1 = VCC2) Analog Supply Voltage _____________ Input RESET, CNVSS, BYTE,...
  • Page 347 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.47 Recommended Operating Conditions (1) Symbol Supply Voltage (VCC1 = VCC2) Analog Supply Voltage Supply Voltage Analog Supply Voltage HIGH Input...
  • Page 348 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.48 Recommended Operating Conditions (2) Symbol f(XIN) Main Clock Input Oscillation No Wait Flash Memory (2) (3) (4) Frequency f(XCIN) Sub Clock Oscillation Frequency...
  • Page 349 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.49 Electrical Characteristics (1) Symbol Parameter HIGH Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,...
  • Page 350 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.50 Electrical Characteristics (2) Symbol Parameter Power Supply Output pins are open Current and other pins are VSS. (VCC = 4.2 to 5.5V) NOTES: 1.
  • Page 351 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.51 A/D Conversion Characteristics Symbol Parameter – Resolution Integral 10 bits Nonlinearity Erro 8 bits – Absolute 10 bits Accuracy 8 bits Differential Nonlinearity Error –...
  • Page 352 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 22.53 Flash Memory Version Electrical Characteristics Symbol Program and Erase Endurance Word Program Time (VCC = 5.0V) Lock Bit Program Time Block Erase Time (VCC = 5.0V)
  • Page 353 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.56 External Clock Input (XIN Input)
  • Page 354 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 22.63 Timer B Input (Counter Input in Event Counter Mode)
  • Page 355 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) XIN input TAiIN input TAiOUT input TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected)

  • Page 356: Usage Precaution

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23. Usage Precaution 23.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read).

  • Page 357: External Bus

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.2 External Bus (Normal-ver. only) When resetting CNVSS pin with "H" input, contents of internal ROM cannot be read out. Rev.2.00 Nov 28, 2005...

  • Page 358: External Clock

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.3 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.

  • Page 359: Pll Frequency Synthesizer

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 22. Electrical characteristics.)

  • Page 360: Power Control

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.5 Power Control • When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
  • Page 361 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) • Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.

  • Page 362: Oscillation Stop, Re-Oscillation Detection Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.6 Oscillation Stop, Re-oscillation Detection Function If the following conditions are all met, the following restriction occur in operation of oscillation stop, re-oscillation stop detection interrupt.

  • Page 363: Protection

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.7 Protection Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”...

  • Page 364: Interrupt

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.8 Interrupt 23.8.1 Reading Address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence.

  • Page 365: Changing Interrupt Generate Factor

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.8.4 Changing Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit of the interrupt control register for the changed interrupt may inadvertently be set to “1”...

  • Page 366: Rewrite Interrupt Control Register

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.8.6 Rewrite Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no interrupt requests may be generated.

  • Page 367: Dmac

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.9 DMAC 23.9.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below.

  • Page 368: Timers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10 Timers 23.10.1 Timer A 23.10.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1”...
  • Page 369 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
  • Page 370 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
  • Page 371 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...

  • Page 372: Timer B

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10.2 Timer B 23.10.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit “1”...
  • Page 373 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.10.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or TBSR register to “1”...

  • Page 374: Thee-Phase Motor Control Timer Function

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.11 Thee-Phase Motor Control Timer Function If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overflow, read the value of TB2 register, verify that there is sufficient time until Timer B2 overflows, before doing an immediate write to TAi-1 register.

  • Page 375: Serial Interface

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.12 Serial Interface 23.12.1 Clock Synchronous Serial I/O Mode 23.12.1.1 Transmission/reception With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L”...

  • Page 376: Special Modes

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.12.2 Special Modes 23.12.2.1 Special Mode 1 (I When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0”...

  • Page 377: Si/Oi

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.12.3 SI/Oi (i = 3 to 6) The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately 10ns may be output when changing the SMi3 bit in the SiC register from “0”...

  • Page 378: A/D Converter

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.13 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs).
  • Page 379 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock.

  • Page 380: Can Module

    23.14.1 Reading CiSTR Register (i = 0, 1) The CAN module on the M16C/6N Group (M16C/6NK, M16C/6NM) updates the status of the CiSTR register in a certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the CPU has the access priority;...
  • Page 381 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) fCAN CPU read signal Updating period of CAN module CPU reset signal CiSTR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initial-...

  • Page 382: Performing Can Configuration

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.14.2 Performing CAN Configuration If the Reset bit in the CiCTLR register (i = 0, 1) is changed from “0” (operation mode) to “1” (reset/ initialization mode) in order to place the CAN module from CAN operation mode into CAN reset/initializa- tion mode, always be sure to check that the State_Reset bit in the CiSTR register is set to “1”...

  • Page 383: Suggestions To Reduce Power Consumption

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.14.3 Suggestions to Reduce Power Consumption When not performing CAN communication, the operation mode of CAN transceiver should be set to “standby mode” or “sleep mode”.

  • Page 384: Can Transceiver In Boot Mode

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.14.4 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode”...

  • Page 385: Programmable I/O Ports

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.15 Programmable I/O Ports If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a high- impedance state.

  • Page 386: Dedicated Input Pin

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.16 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs. When different power supplied to the system, and input voltage of unused dedicated input pin is larger than voltage of VCC pin, connect dedicated input pin to VCC via resistor (approximately 1kΩ).

  • Page 387: Electrical Characteristic Differences Between Mask Rom And Flash Memory Version Microcomputers

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.17 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.

  • Page 388: Mask Rom Version

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.18 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area. Rev.2.00 Nov 28, 2005 page 370 of 378 REJ09B0124-0200 23.

  • Page 389: Flash Memory Version

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.19 Flash Memory Version 23.19.1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh.

  • Page 390: Prohibited Instructions

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.19.9 Prohibited Instructions The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction 23.19.10 Interrupt...

  • Page 391: Flash Memory Programming Using Boot Program

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.20 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program, be careful about the pins state and connection as follows.

  • Page 392: Noise

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 23.21 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and VSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 23.11 shows the bypass capacitor connection.

  • Page 393: Appendix 1. Package Dimensions

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions JEITA Package Code RENESAS Code P-LQFP100-14x14-0.50 PLQP0100KB-A Index mark JEITA Package Code RENESAS Code P-LQFP128-14x20-0.50 PLQP0128KB-A Index mark Rev.2.00...
  • Page 394 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memo Rev.2.00 Nov 28, 2005 page 376 of 378 REJ09B0124-0200 Appendix 1. Package Dimensions...

  • Page 395: Register Index

    Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Register Index AD0 to AD7 ... 205 ADCON0 ... 204,207,209,211,213,215 ADCON1 ... 204,207,209,211,213,215 ADCON2 ... 205 ADIC ... 86 AIER ... 100 AIER2 ...
  • Page 396 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) U0BCNIC to U2BCNIC ... 86 U0BRG to U2BRG ... 153 U0C0 to U2C0 ... 154 U0C1 to U2C1 ... 155 U0MR to U2MR ... 154 U0RB to U2RB ...
  • Page 397 Figure 18.8 C0STR and C1STR Registers (lower) • State_LoopBack bit: The expression of Function is revised. • State_BasicCAN bit: The expression of Function is revised. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description : Unit is revised from “V” to “mA”.
  • Page 398 • NOTE 1 is added. 35 to 37 5. Reset: Layout is changed. Figure 5.2 Reset Sequence is revised. Table 5.1 Pin Status When RESET Pin Level is “L” is revised. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Summary is revised from “L = –200µA”...
  • Page 399 Table 12.1 DMAC Specifications: DMA transfer Cycles is added. 12.1 Transfer Cycle: 3rd and 4th sentences (During ... / Furthermore ...) are revised 12.1.2 Effect of BYTE Pin Level is added. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Values and Processor Modes are added.
  • Page 400 Figure20.7 PDi Registers (upper): NOTE 2 is added. Figure20.8 Pi Registers (upper): NOTE 2 is added. Figure20.9 PUR0 Register (upper): NOTE 1 is added. Figure20.9 PUR1 Register (middle): NOTES 1, 2 and 3 are added. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Summary ________...
  • Page 401 Table 21.8 Pin Functions for CAN I/O Mode • Description of VCC1, VCC2, VSS is revised. • Description of P8_4 is revised. • NOTE 1 is added. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Mode (Normal-ver. only) is added. dissipation mode” is addded.
  • Page 402 23.15 Programmable I/O Ports: 5th and 6th items (Indeterminate values ... / When the 23.19.2 Stop Mode is revised. 23.19.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation 23.19.8 Operation Speed is revised. M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description stop mode ...) are revised. PM01 ...) are added.
  • Page 403 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.2.00 Nov 28, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
  • Page 404 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

This manual is also suitable for:

M16c/6nm

Table of Contents