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M16C/5L Group, M16C/56 Group
Table 15.7
Registers and Settings in Timer Mode
Register
PCLKR
CPSRF
TCKDIVC0
PWMFS
TACS0 to TACS2
TAPOFS
TAOW
TAi1
TABSR
ONSF
TA0TGH to TA0TGL Set to 00b.
TRGSR
UDF
TAi
TAiMR
i = 0 to 4
Note:
1.
This table does not describe a procedure.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bit
PCLK0
Select the count source.
CPSR
Write 1 to reset the clock prescaler.
TCDIV00
Select the clock used prior to timer AB frequency dividing.
PWMFSi
Set to 0.
7 to 0
Select the count source.
Select the output polarity when the MR0 bit in the TAiMR register
POFSi
is 1 (pulse output).
TAiOW
Set to 0.
15 to 0
- (does not need to be set)
Set to 1 when starting counting.
TAiS
Set to 0 when stopping counting.
TAiOS
Set to 0.
TAZIE
Set to 0.
TAiTGH to TAiTGL Set to 00b.
TAiUD
Set to 0.
TAiP
Set to 0.
15 to 0
Set the counter value.
7 to 0
Refer to the TAiMR register below
(1)
Function and Setting
15. Timer A
Page 249 of 803
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