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REVISION HISTORY
Rev.
Date
1.00
Jan. 31, 2010 Watchdog Timer
DMAC
Timer A
Timer B
Timer S
Serial Interface UARTi (i = 0 to 4)
Multi-Master I
M16C/5L Group, M16C/56 Group Hardware Manual
Page
Table 13.1 "Watchdog Timer Specification" "Dedicated 125-kHz on-chip oscillator for
210
watchdog timer" added to fWDT
Figure 13.1 "Watchdog Timer Block Diagram" "Dedicated 125-kHz on-chip oscillator for
211
watchdog timer" added; Typos corrected from "WDTC" to "WDC"
"WDTUFS1 to WDTUFS0 (Watchdog Timer Initial Set Bit) (b0-b1)" typo corrected from
217
"CSPR0" to "CSPRO"
220
13.4.3 "Count Source Protect Mode Enabled" description added below Table 13.4
Table 14.4 "DMA Request Sources for DMA1" "Both edges of INT1 " moved to 00111b
231
Table 14.5 "DMA Request Sources for DMA2" "Both edges of INT2" moved to 00110b
232
233
14.3.2 "DMA Request" "interrupts" in the 12th line modified to "the interrupt control registers"
Figure 15.2 "Timer A Configuration" "programmable output mode" deleted from Timer A0 and
243
Timer A3
"TA0TGH and TA0TGL (Timer A0 Event/Trigger Select Bit) (b7-b6)" typo corrected from
255
"TA0GH to TA0GL" to "TA0TGH to TA0TGL"
Table 15.9 "Registers and the Setting in Event Counter Mode (When Not Processing Two-
Phase Pulse Signal)
266
(When Processing Two-Phase Pulse Signal)
TACS2, and ONSF (TAiTGH to TAiTGL) modified to "- (setting unnecessary)"
Table 16.8 "Registers and the Setting in Event Counter Mode
309
TCKDIVC0, and TBCS0 to TBCS1 modified to "- (setting unnecessary)"
Table 16.9 "Specifications of Pulse Period/Pulse Width Measurement Modes" specification for
312
"Write to timer" the second bullet deleted
—
"phase-delayed waveform" modified to "inverted waveform"
Description of INT5 and IDU deleted
—
362
Table 18.1 "IC/OC Specifications" Specifications for Channel interrupts modified
368
"MOD1 and MOD0 (Operating Mode Select Bit) (b1-b0)" the second line modified
371
18.2.5 "Base Timer Register (G1BT)" description added to function
Table 18.5 "Base Timer Specifications" "while the base timer is counting" added to "Base
384
timer reset value"; "and the BTS bit is 0" added to function for "Read from base timer" and
"Write to base timer"
Table 18.14 "Inverted Waveform Output Mode Specifications" "single-waveform" "single-phase
399
waveform" in specifications for "Selectable functions" modified to "inverted waveform"
Table 18.15 "SR Waveform Output Mode Specifications" "(n>m)" added to specifications for
402
output waveform; "single-phase waveform" in specifications for selectable function modified to
"SR waveform"; Note 1 deleted
21.1 "Registers" description for registers revised; Table 21.1 "Registers (1/2)" added; Register
448-462
diagrams revised
449
21.1.1 "Peripheral Clock Select Register (PCLKR)" added
479
Table 21.11 "I/O Pin Functions in I
2
Table 21.14 "I
C Mode Functions" description for "Store received data" moved to "Read
482
received data"
488
Table 21.16 "Special Mode 2 Specifications" note 1 deleted
489
Table 21.17 "I/O Pin Functions in Special Mode 2" added
491
21.5.1 "Clock Phase Setting Function" the sixth and seventh lines deleted
Diagrams for "Transmit and Receive Timing (CKPH = 0) in Slave Mode (External Clock)" and
491
"Transmit and Receive Timing (CKPH = 1) in Slave Mode (External Clock)" deleted
499
21.8.1.3 "Reception" typo corrected from "the RE bit" to "the RI bit" in the third paragraph
2
C-bus Interface
Table 22.1 "Multi-Master I
501
selectable functions modified
502
Table 22.2 "Detections by I
507
"BC2 to BC0 (Bit counter) (b2 to b0)" description modified
"WIT (Data Receive Interrupt Enable Bit) (b1)" "slave address transmission/reception" in the
515
12th line modified to "slave address reception"
Revision History
(1)
" and Table 15.11 "Registers and the Setting in Event Counter Mode
(1)
" setting for PCLKR, TCKDIVC0, TACS0 to
2
C Mode" added
2
C Interface Specifications" description for "Timeout detection" in
2
C Interface" function for slave address match modified
C- 22
(1)
" setting for PCLKR,
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