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M16C/5L Group, M16C/56 Group
P0_2 / AN0_2
P0_1 / AN0_1
P0_0 / AN0_0
P10_7 / AN_7 / KI3
P10_6 / AN_6 / KI2
P10_5 / AN_5 / KI1
P10_4 / AN_4 / KI0
P10_3 / AN_3
P10_2 / AN_2
P10_1 / AN_1
P10_0 / AN_0
P9_3 / AN2_4 /CTX0
P9_2 / AN3_2 / TB2IN / CRX0
Note:
1. Pins CTX0 and CRX0 are only available in the M16C/5L Group.
Figure 1.6
Pin Assignment for 64-Pin Package (Top View)
Set bits PACR2 to PACR0 in the PACR register to 010b before signals are input or output to individual
pins after reset. When the PACR register is not set, signals are not input or output for some of the pins.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
49
50
51
52
M16C/5L Group
53
M16C/56 Group
54
55
56
PLQP0064KB-A
57
58
(64P6Q-A)
AVSS
59
60
(Top view)
VREF
61
AVCC
62
(1)
63
(1)
64
P3_0 / CLK3
32
P3_1 / RXD3
31
P3_2 / TXD3
30
P3_3 / CTS3 / RTS3
29
P6_4 / RTS1 / CTS1
28
P6_5 / CLK1
27
P6_6 / RXD1
26
P6_7 / TXD1
25
P7_0 / TXD2 / SDA2 / TA0OUT / CTS1 / RTS1
24
P7_1 / RXD2 / SCL2 / TA0IN / CLK1
23
P7_2 / CLK2 / TA1OUT / V / RXD1
22
P7_3 / CTS2 / RTS2 / TA1IN / V / TXD1
21
P7_4 / TA2OUT / W
20
P7_5 / TA2IN / W
19
P7_6 / TA3OUT
18
17
P7_7 / TA3IN
1. Overview
Page 13 of 803
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