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9.3.1
Normal Operating Mode .................................................................................................. 122
9.3.2
Clock Mode Transition Procedure ................................................................................... 126
9.3.3
Wait Mode ....................................................................................................................... 129
9.3.4
Stop Mode ....................................................................................................................... 131
9.4
Power Control in Flash Memory ............................................................................................... 133
9.4.1
Stopping Flash Memory ................................................................................................... 133
9.4.2
Reading Flash Memory ................................................................................................... 134
9.5
Reducing Power Consumption ................................................................................................. 136
9.5.1
Ports ................................................................................................................................ 136
9.5.2
A/D Converter .................................................................................................................. 136
9.5.3
Stopping Peripheral Functions ......................................................................................... 136
9.5.4
Switching the Oscillation-Driving Capacity ...................................................................... 136
9.6
Notes on Power Control............................................................................................................ 137
9.6.1
CPU Clock ....................................................................................................................... 137
9.6.2
Wait Mode ....................................................................................................................... 137
9.6.3
Stop Mode ....................................................................................................................... 137
9.6.4
Low Current Consumption Read Mode ........................................................................... 138
9.6.5
Slow Read Mode ............................................................................................................. 138
10. Processor Mode ................................................................................... 139
10.1
Introduction ............................................................................................................................... 139
10.2
Registers................................................................................................................................... 140
10.2.1
Processor Mode Register 1 (PM1) .................................................................................. 140
10.2.2
Program 2 Area Control Register (PRG2C) .................................................................... 141
10.2.3
Flash Memory Control Register 1 (FMR1) ....................................................................... 142
10.3
Software Wait............................................................................................................................ 143
10.4
Bus Hold ................................................................................................................................... 143
11. Programmable I/O Ports....................................................................... 144
11.1
Introduction ............................................................................................................................... 144
11.2
I/O Ports and Pins..................................................................................................................... 145
11.3
Registers................................................................................................................................... 152
11.3.1
NMI Digital Debounce Register (NDDR) ......................................................................... 153
11.3.2
P1_7 Digital Debounce Register (P17DDR) .................................................................... 153
11.3.3
Pull-Up Control Register 0 (PUR0) .................................................................................. 154
11.3.4
Pull-Up Control Register 1 (PUR1) .................................................................................. 154
11.3.5
Pull-Up Control Register 2 (PUR2) .................................................................................. 155
11.3.6
Port Control Register (PCR) ............................................................................................ 156
11.3.7
Input Threshold Select Register 0 (VLT0) ....................................................................... 157
11.3.8
Input Threshold Select Register 1 (VLT1) ....................................................................... 158
11.3.9
Input Threshold Select Register 2 (VLT2) ....................................................................... 158
A- 4
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