Renesas M16C Series Hardware Manual
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Renesas M16C Series Hardware Manual

Renesas M16C Series Hardware Manual

16-bit microcopmuter
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REJ09B0062-0120
16
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 1.20
Revision date: Jan 27, 2006
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
R8C/11 Group
Hardware Manual
M16C FAMILY/R8C/Tiny SERIES
www.renesas.com

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  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
  • Page 2 Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp.

  • Page 3: How To Use This Manual

    How to Use This Manual Introduction This hardware manual provides detailed information on the R8C/11 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. X X X r e g i s t e r S y m b o l A d d r e s s...
  • Page 4 • Introduction to the basic functions in the M16C family • Programming method with Assembly and C languages Preliminary report about the specification of a product, a document, RENESAS TECHNICAL UPDATE etc. NOTES: 1. Before using this material, please visit the our website to verify that this is the most updated...

  • Page 5: Table Of Contents

    Table of Contents SFR Page Reference Chapter 1. Overview .............. 1 1.1 Applications ........................1 1.2 Performance Overview ....................2 1.3 Block Diagram ........................ 3 1.4 Product Information ....................... 4 1.5 Pin Assignments......................5 1.6 Pin Description ....................... 6 Chapter 2. Central Processing Unit (CPU) ......7 2.1 Data Registers (R0, R1, R2 and R3) ................
  • Page 6 5.4 Voltage Detection Circuit ..................... 21 5.4.1 Voltage Detection Interrupt ........................26 5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt ................. 28 Chapter 6. Clock Generation Circuit........29 6.1 Main Clock ........................34 6.2 On-Chip Oscillator Clock ..................... 35 6.2.1 Low-Speed On-Chip Oscillator ......................
  • Page 7 12.1.2 Pulse Output Mode ..........................74 12.1.3 Event Counter Mode ........................... 75 12.1.4 Pulse Width Measurement Mode ....................... 76 12.1.5 Pulse Period Measurement Mode ..................... 78 12.2 Timer Y......................... 80 12.2.1 Timer Mode ............................83 12.2.2 Programmable Waveform Generation Mode ..................85 12.3 Timer Z .........................
  • Page 8 17.1 Overview ........................164 17.2 Memory Map ......................165 17.3 Functions To Prevent Flash Memory from Rewriting..........166 17.3.1 ID Code Check Function ........................166 17.4 CPU Rewrite Mode ....................167 17.4.1 EW0 Mode ............................168 17.4.2 EW1 Mode ............................168 17.4.3 Software Commands ........................
  • Page 9 Appendix 1 Package Dimensions ........199 Appendix 2 Connecting Examples for Serial Writer and On-chip Debugging Emulator .......... 200 Appendix 3 Example of Oscillation Evaluation Circuit .. 202 Register Index ..............203...
  • Page 10 SFR Page Reference P a g e R e g i s t e r S y m b o l S y m b o l P a g e A d d r e s s R e g i s t e r A d d r e s s 0 0 4 0 0 0 0 0...
  • Page 11 SFR Page Reference Symbol P a g e Register S y m b o l P a g e A d d r e s s R e g i s t e r A d d r e s s A D r e g i s t e r 1 2 7 0 0 C 0...

  • Page 12: Chapter 1. Overview

    R8C/11 Group REJ09B0062-0120 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.20 Jan 27, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency.

  • Page 13: Performance Overview

    R8C/11 Group 1. Overview 1.2 Performance Overview Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance Number of basic instructions 89 instructions Minimum instruction execution time 50 ns (f(X ) = 20 MH = 3.0 to 5.5 V) 100 ns (f(X ) = 10 MH = 2.7 to 5.5 V)

  • Page 14: Block Diagram

    R8C/11 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows this MCU block diagram. I / O p o r t P o r t P 3 Port P4 P o r t P 0 Port P1 Pe r i p h e r a l f u n c t i o n s T i m e r A / D c o n v e r t e r ( 1 0 b i t s...

  • Page 15: Product Information

    2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/11 group R8C/Tiny series Memory type: F: Flash memory version Renesas MCU Renesas semiconductors Figure 1.2 Type No., Memory Size, and Package Rev.1.20 Jan 27, 2006 page 4 of 204 REJ09B0062-0120...

  • Page 16: Pin Assignments

    R8C/11 Group 1. Overview 1.5 Pin Assignments Figure 1.3 shows the pin configuration (top view). PIN CONFIGURATION (top view) 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 / A N /INT /CMP0 /CMP0 / A N MODE...

  • Page 17: Pin Description

    R8C/11 Group 1. Overview 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Pin name I/O type Function Power supply Vcc, Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the input Vss pin.

  • Page 18: Chapter 2. Central Processing Unit (Cpu)

    R8C/11 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided. b 3 1 b 1 5 b 8 b7...

  • Page 19: Address Registers (A0 And A1)

    R8C/11 Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0).

  • Page 20: Chapter 3. Memory

    R8C/11 Group 3. Memory 3. Memory Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses 00000 to FFFFF The internal ROM is allocated lower addresses beginning with address 0FFFF . For example, a 16-Kbyte internal ROM is allocated addresses from 0C000 to 0FFFF The fixed interrupt vector table is allocated addresses 0FFDC...

  • Page 21: Chapter 4. Special Function Registers (Sfr)

    R8C/11 Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information(1) R e g i s t e r Symbol After reset Address...
  • Page 22 R8C/11 Group 4. Special Function Register (SFR) Table 4.2 SFR Information(2) R e g i s t e r Symbol A f t e r r e s e t A d d r e s s 0 0 4 0 0 0 4 1 0 0 4 2 0 0 4 3...
  • Page 23 R8C/11 Group 4. Special Function Register (SFR) Table 4.3 SFR Information(3) R e g i s t e r Symbol A f t e r r e s e t A d d r e s s T i m e r Y , Z m o d e r e g i s t e r T Y Z M R 0 0 8 0 P r e s c a l e r Y r e g i s t e r...
  • Page 24 R8C/11 Group 4. Special Function Register (SFR) R e g i s t e r A d d r e s s Symbol After reset 0 0 C 0 A D r e g i s t e r 0 0 C 1 0 0 C 2 0 0 C 3 0 0 C 4...

  • Page 25: Chapter 5. Reset

    R8C/11 Group 5.1 Hardware Reset 5. Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 5.1 Hardware Reset There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU.
  • Page 26 R8C/11 Group 5.1 Hardware Reset 0000 Data register(R0) 0000 Data register(R1) 0000 Data register(R2) 0000 Data register(R3) 0000 Address register(A0) 0000 Address register(A1) 0000 Frame base register(FB) 00000 Interrupt table register(INTB) Content of addresses 0FFFE to 0FFFC Program counter(PC) 0000 User stack pointer(USP) 0000 Interrupt stack pointer(ISP)
  • Page 27 R8C/11 Group 5.1 Hardware Reset 2 . 7 V R E S E T RESET Equal to or less than 0.2V M o r e t h a n t d ( P - R ) + 5 0 0 µ s a r e n e e d e d .

  • Page 28: Hardware Reset 2

    R8C/11 Group 5.1 Hardware Reset 5.1.2 Hardware Reset 2 This is the reset generated by the voltage detection circuit which is built-in to the microcomputer. The voltage detection circuit monitors the input voltage at Vcc input pin. The microcomputer is reset when the voltage at the V input pin drops below Vdet if all of the following conditions hold true.

  • Page 29: Power-On Reset Function

    R8C/11 Group 5.1 Hardware Reset 5.1.3 Power-on Reset Function The power-on reset is the function which can reset the microcomputer without the external reset ____________ circuit. The RESET pin should be connected to the V pin via about 5 kΩ pull-up resistance using the power-on reset function, the function turns to active and the microcomputer has its pins, CPU and ____________ SFR initialized.
  • Page 30 R8C/11 Group 0.1V to 2.7V RESET RESET 0.8V or above about 5 kΩ within td(P-R) det 3 det (3) cc min por2 por1 Sampling time (1, 2) w(por2) w(Vpor2 –Vdet) w(por1) w(Vpor1–Vdet) Internal reset signal (“L” effective) X 32 X 32 RING-S RING-S NOTES:...

  • Page 31: Software Reset

    R8C/11 Group 5.2 Software Reset, 5.3 Watchdog Timer Reset 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector.

  • Page 32: Voltage Detection Circuit

    R8C/11 Group 5.4 Voltage Detection Circuit 5.4 Voltage Detection Circuit The voltage detection circuit monitors the input voltage at the V pin with respect to Vdet. The user program can check for voltage detection using the VC13 bit or set up the voltage detection interrupt register to generate a hardware reset 2 or voltage detection interrupt.
  • Page 33 R8C/11 Group 5.4 Voltage Detection Circuit V o l t a g e d e t e c t i o n r e g i s t e r 1 (2 ) S y m b o l A d d r e s s A f t e r r e s e t 0 0 0 0 0 0 0...
  • Page 34 R8C/11 Group Voltage detection interrupt register Symbol Address After reset (10) D4INT 001F Reset input : 00 RESET pin = "H" retaining : 01000001 B i t s y m b o l Bit name V o l t a g e d e t e c t i o n i n t e r r u p t D 4 0 Disable (7 )
  • Page 35 R8C/11 Group 5.4 Voltage Detection Circuit 5.0 V 5.0 V x 32 Sampling time fRING (3 to 4 clock) Internal reset signal (D46 bit=1) VC13 bit Set to“1” by program (voltage detection circuit enabled) VC27 bit Interrupt acknowledged Interrupt acknowledged Sampling time Voltage detection (3 to 4 clock)
  • Page 36 R8C/11 Group 5.4 Voltage Detection Circuit 5.0V Internal reset signal(D46 bit = 1) VC13 bit Set to "1" by program (voltage detection circuit enabled) VC27 bit CM 10 bit Interrupt acknowledged Voltage detection interrupt request (D46 bit = 0) The above applies to the following conditions. CM10 : CM1 register bit D4INT register D40 = 1 (voltage detection interrupt enabled) VC13 : VCR1 register bit...

  • Page 37: Voltage Detection Interrupt

    R8C/11 Group 5.4.1 Voltage Detection Interrupt Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit. Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to the voltage detection interrupt. A voltage detection interrupt is generated when the input voltage at the V pin rises to Vdet or more or drops below Vdet if all of the following conditions hold true in normal operation mode and wait...
  • Page 38 R8C/11 Group Rev.1.20 Jan 27, 2006 page 27 of 204 REJ09B0062-0120...
  • Page 39 R8C/11 Group Rev.1.20 Jan 27, 2006 page 28 of 204 REJ09B0062-0120...

  • Page 40: Chapter 6. Clock Generation Circuit

    R8C/11 Group 6. Clock Generating Circuit 6. Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: • Main clock oscillation circuit • On-chip oscillator (with oscillation stop detection function) Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows the clock generation circuit. Figures 6.2 to 6.4 show the clock-related registers.
  • Page 41 R8C/11 Group 6. Clock Generating Circuit H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1 ( 7 - b i t ) R I N G - f a s t F r e q u e n c y a d j u s t a b l e O n - c h i p...
  • Page 42 R8C/11 Group S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( 1 ) S y m b o l A d d r e s s A f t e r r e s e t C M 0 0 0 0 6...
  • Page 43 R8C/11 Group 6. Clock Generating Circuit O s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e r ( 1 ) Symbol Address After reset...
  • Page 44 R8C/11 Group 6. Clock Generating Circuit H i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0 ( 3 ) S y m b o l A d d r e s s...

  • Page 45: Main Clock

    R8C/11 Group 6.1 Main Clock The following describes the clocks generated by the clock generation circuit. 6.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks.

  • Page 46: On-Chip Oscillator Clock

    R8C/11 Group 6.2 On-chip Oscillator Clock 6.2 On-chip Oscillator Clock This clock is supplied by an on-chip oscillator. There are two kinds of on-chip oscillator: high-speed on- chip oscillator and low-speed on-chip oscillator. These oscillators are selected by the bit HR01 bit in the HR0 register.

  • Page 47: Cpu Clock And Peripheral Function Clock

    R8C/11 Group 6.3 CPU Clock and Peripheral Function Clock 6.3 CPU Clock and Peripheral Function Clock There are two types of clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions. Also refer to “Figure 6.1 Clock Generation Circuit”. 6.3.1 CPU Clock This is an operating clock for the CPU and watchdog timer.

  • Page 48: Power Control

    R8C/11 Group 6.4 Power Control 6.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as normal operation mode. 6.4.1 Normal Operation Mode Normal operation mode is further classified into four modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
  • Page 49 R8C/11 Group 6.4 Power Control Table 6.2 Setting Clock Related Bit and Modes O C D r e g i s t e r CM1 register C M 0 r e g i s t e r M o d e s OCD2 C M 1 7 , C M 1 6 C M 1 3...

  • Page 50: Wait Mode

    R8C/11 Group 6.4 Power Control 6.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are operated by the CPU clock. Because the main clock and on-chip oscillator clock both are on, the peripheral functions using these clocks keep operating.

  • Page 51: Stop Mode

    R8C/11 Group 6.4 Power Control 6.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
  • Page 52 R8C/11 Group 6.4 Power Control Figure 6.6 shows the state transition of power control. Reset Low-speed On-chip Oscillator Mode OCD2=1 HR01=0 CM14=0 There are six power control modes. (1) High-speed mode (2) Middle-speed mode (3) High-speed on-chip oscillator mode High-speed Mode, (4) Low-speed on-chip oscillator mode Middle-speed mode (5) Wait mode...

  • Page 53: Oscillation Stop Detection Function

    R8C/11 Group 6.5 Oscillation Stop Detection Function 6.5 Oscillation Stop Detection Function The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD register.
  • Page 54 R8C/11 Group Rev.1.20 Jan 27, 2006 page 43 of 204 REJ09B0062-0120...

  • Page 55: Chapter 7. Protection

    R8C/11 Group 7. Protection 7. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected by the PRCR register.

  • Page 56: Chapter 8. Processor Mode

    R8C/11 Group 8. Processor Mode 8. Processor Mode 8.1 Types of Processor Mode The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register. Table 8.1 Features of Processor Mode Processor mode Access space Pins which are assigned I/O ports...

  • Page 57: Chapter 9. Bus

    R8C/11 Group 9. Bus 9. Bus During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units.

  • Page 58: Chapter 10. Interrupt

    R8C/11 Group 10.1 Interrupt Overview 10. Interrupt 10.1 Interrupt Overview 10.1.1 Type of Interrupts Figure 10.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (Non-maskable interrupt) INT instruction Interrupt Watchdog timer Oscillation stop detection Special Voltage detection (Non-maskable interrupt)

  • Page 59: Software Interrupts

    R8C/11 Group 10.1 Interrupt Overview 10.1.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non- maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow).

  • Page 60: Hardware Interrupts

    R8C/11 Group 10.1 Interrupt Overview 10.1.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function inter- rupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. • Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer.

  • Page 61: Interrupts And Interrupt Vector

    R8C/11 Group 10.1 Interrupt Overview 10.1.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec- tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
  • Page 62 R8C/11 Group 10.1 Interrupt Overview • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table. Table 10.2 Vector Tables (1 ) Software interrupt...

  • Page 63: Interrupt Control

    R8C/11 Group 10.1 Interrupt Overview 10.1.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/ disable the maskable interrupts.
  • Page 64 R8C/11 Group 10.1 Interrupt Overview I n t e r r u p t c o n t r o l r e g i s t e r ( 2 ) S y m b o l A d d r e s s A f t e r r e s e t K U P I C 0 0 4 D...
  • Page 65 R8C/11 Group 10.1 Interrupt Overview • I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. • IR Bit The IR bit is set to “1”...
  • Page 66 R8C/11 Group 10.1 Interrupt Overview • Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
  • Page 67 R8C/11 Group 10.1 Interrupt Overview • Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the inter- rupt routine is executed.
  • Page 68 R8C/11 Group 10.1 Interrupt Overview • Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first.
  • Page 69 R8C/11 Group 10.1 Interrupt Overview • Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
  • Page 70 R8C/11 Group 10.1 Interrupt Overview • Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 10.9 shows the Interrupts Priority Select Circuit. H i g h e s t P r i o r i t y l e v e l o f e a c h i n t e r r u p t L e v e l 0 ( d e f a u l t v a l u e ) Compare 0...

  • Page 71: Int Interrupt

    ______ R8C/11 Group 10.2 INT Interrupt ______ 10.2 INT Interrupt ________ 10.2.1 INT0 Interrupt _______ INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN register and the POL bit in the INT0IC register.
  • Page 72 R8C/11 Group Rev.1.20 Jan 27, 2006 page 61 of 204 REJ09B0062-0120...

  • Page 73: Int1 Interrupt And Int2 Interrupt

    ______ R8C/11 Group 10.2 INT Interrupt ______ ______ 10.2.3 INT1 Interrupt and INT2 Interrupt ______ ______ INT1 interrupts are triggered by INT1 inputs. The edge polarity is selected with the R0EDG bit in the ______ TXMR register. The INT1 pin is shared with the CNTR0 pin. ______ ______ INT2 interrupts are triggered by INT2 inputs.

  • Page 74: Int3 Interrupt

    ______ R8C/11 Group 10.2 INT Interrupt ______ 10.2.4 INT3 Interrupt _____ ______ INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to “0” ______ _______ (INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register.
  • Page 75 ______ R8C/11 Group 10.2 INT Interrupt T i m e r C c o n t r o l r e g i s t e r 0 S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 T C C 0...

  • Page 76: Key Input Interrupt

    R8C/11 Group 10.3 Key Input Interrupt 10.3 Key Input Interrupt _____ _____ A key input interrupt is generated on an input edge of any of the K1 to K1 pins. Key input interrupts can _____ be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled selecting with the KIiEN (i=0 to 3) bit in the KIEN register.

  • Page 77: Address Match Interrupt

    R8C/11 Group 10.4 Address Match Interrupt 10.4 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the AIER0 and AIER1 bits in the AIER register to enable or disable the interrupt.
  • Page 78 R8C/11 Group 10.4 Address Match Interrupt Address match interrupt enable register Symbol Address After reset AIER 0009 XXXXXX00 Bit symbol Bit name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled Address match interrupt 1 AIER1 0 : Interrupt disabled enable bit...

  • Page 79: Chapter 11. Watchdog Timer

    R8C/11 Group 11. Watchdog Timer 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.

  • Page 80: Watchdog Timer

    R8C/11 Group 11. Watchdog Timer W a t c h d o g t i m e r c o n t r o l r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t W D C 0 0 0 1 1 1 1 1...

  • Page 81: Chapter 12. Timers

    R8C/11 Group 12. Timers 12. Timers The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has input capture and output compare.
  • Page 82 R8C/11 Group T X C K 1 t o T X C K 0 = 0 0 P o l a r i t y s w i t c h i n g Toggle flip-flop Rev.1.20 Jan 27, 2006 page 71 of 204 REJ09B0062-0120...

  • Page 83: Timer X

    R8C/11 Group Prescaler X Register Symbol Address After reset PREX 008C Function Setting range to FF Twmf 0 6211h5.070. 1164 Internal count source is counted to FF Internal count source is counted to FF Externally input pulses are counted to FF Pulse width of externally input pulses is measured to FF...

  • Page 84: Timer Mode

    R8C/11 Group 12.1 Timer (Timer X) 12.1.1 Timer Mode In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode Specifications”). Figure 12.4 shows the TXMR register in timer mode. Table 12.2 Timer Mode Specifications Item Specification Count source...

  • Page 85: Pulse Output Mode

    R8C/11 Group 12.1 Timer (Timer X) 12.1.2 Pulse Output Mode In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode Specifications”).

  • Page 86: Event Counter Mode

    R8C/11 Group 12.1 Timer (Timer X) 12.1.3 Event Counter Mode In this mode, the timer counts an external signal fed to INT1/CNTR pin (See “Table 12.4 Event Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode. Table 12.4 Event Counter Mode Specifications Item Specification Count source...

  • Page 87: Pulse Width Measurement Mode

    R8C/11 Group 12.1 Timer (Timer X) 12.1.4 Pulse Width Measurement Mode In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See “Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register in pulse width measurement mode.
  • Page 88 R8C/11 Group n = high-level: the contents of TX register, low-level: the contents of PREX register FFFF Count stop 0000 Rev.1.20 Jan 27, 2006 page 77 of 204 REJ09B0062-0120...

  • Page 89: Pulse Period Measurement Mode

    R8C/11 Group 12.1 Timer (Timer X) 12.1.5 Pulse Period Measurement Mode In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See “Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register in pulse period measurement mode.
  • Page 90 R8C/11 Group 12.1 Timer (Timer X) U n d e r f l o w s i g n a l o f p r e s c a l e r X S e t t o " 1 " b y p r o g r a m “...

  • Page 91: Timer Y

    R8C/11 Group 12.2 Timer Y Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show the TYZMR, PREY, TYSC, TYPR, TYZOC, PUM, and YCSS registers.
  • Page 92 R8C/11 Group 12.2 Timer (Timer Y) Prescaler Y register Symbol Address After reset PREY 0081 Mode Function Setting range Internal count source or CNTR1 Timer mode to FF input is counted Programmable Internal count source is counted waveform generation to FF mode Timer Y secondary register Symbol...
  • Page 93 R8C/11 Group T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 S y m b o l A d d r e s s A f t e r r e s e t...

  • Page 94: Timer Mode

    R8C/11 Group 12.2 Timer (Timer Y) 12.2.1 Timer Mode In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer mode.
  • Page 95 R8C/11 Group 12.2 Timer (Timer Y) T i m e r Y , Z m o d e r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Y Z M R 0 0 8 0...

  • Page 96: Programmable Waveform Generation Mode

    R8C/11 Group 12.2 Timer (Timer Y) 12.2.2 Programmable Waveform Generation Mode In this mode, an signal output from the TY pin is inverted each time the counter underflows, while the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Program- mable Waveform Generation Mode Specifications”).
  • Page 97 R8C/11 Group 12.2 Timer (Timer Y) T i m e r Y , Z m o d e r e g i s t e r b 7 b 6 b 5 b 4 b 3 b2 b1 b0 S y m b o l A d d r e s s A f t e r r e s e t T Y Z M R...
  • Page 98 R8C/11 Group 12.2 Timer (Timer Y) Set to "1" by program "1" TYS bit in TYZMR register "0" Count starts Count source Prescaler Y underflow signal Timer Y Timer Y secondary primary reloads reloads Contents of Timer Y Set to "0" when interrupt request is accepted, or set by program "1"...

  • Page 99: Timer Z

    R8C/11 Group 12.3 Timer (Timer Z) 12.3 Timer Z Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR, PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers.
  • Page 100 R8C/11 Group 12.3 Timer (Timer Z) P r e s c a l e r Z r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t P R E Z 0 0 8 5 M o d e...
  • Page 101 R8C/11 Group 12.3 Timer (Timer Z) T i m e r Y , Z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 S y m b o l A d d r e s s...

  • Page 102: Timer Mode

    R8C/11 Group 12.3 Timer (Timer Z) 12.3.1 Timer Mode In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table 12.9 Timer Mode Specifications”). The TZSC register is unused in timer mode. Figure 12.22 shows the TYZMR register and PUM register in timer mode.
  • Page 103 R8C/11 Group 12.3 Timer (Timer Z) T i m e r Y , Z m o d e r e g i s t e r b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 S y m b o l A d d r e s s A f t e r r e s e t...

  • Page 104: Programmable Waveform Generation Mode

    R8C/11 Group 12.3 Timer (Timer Z) 12.3.2 Programmable Waveform Generation Mode In this mode, an signal output from the TZ pin is inverted each time the counter underflows, while the values in the TZPR register and TZSC register are counted alternately (see “Table 12.10 Program- mable Waveform Generation Mode Specifications”).
  • Page 105 R8C/11 Group 12.3 Timer (Timer Z) T i m e r Y , Z m o d e r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 T Y Z M R 0 0 8 0...

  • Page 106: Programmable One-Shot Generation Mode

    R8C/11 Group 12.3 Timer (Timer Z) 12.3.3 Programmable One-shot Generation Mode In this mode, upon program command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZ pin (see “Table 12.11 Programmable One-shot Generation Mode Specifications”).
  • Page 107 R8C/11 Group 12.3 Timer (Timer Z) T i m e r Y , Z m o d e r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Y Z M R 0 0 8 0...
  • Page 108 R8C/11 Group 12.3 Timer (Timer Z) “ ” Set to by program “1” TZS bit in TYZMR register “0” “ ” Set to when count “ ” Set to by INT “ ” Set to by program completes input trigger “1”...

  • Page 109: Programmable Wait One-Shot Generation Mode

    R8C/11 Group 12.3 Timer (Timer Z) 12.3.4 Programmable Wait One-shot Generation Mode _______ In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZ pin after waiting for a given length of time (see “Table 12.12 Programmable Wait One-shot Generation Mode Specifications”).
  • Page 110 R8C/11 Group 12.3 Timer (Timer Z) T i m e r Y , Z m o d e r e g i s t e r S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 T Y Z M R 0 0 8 0...
  • Page 111 R8C/11 Group 12.3 Timer (Timer Z) “ ” Set to by program “ 1 ” T Z S b i t i n T Y Z M R r e g i s t e r “ 0 ” “ ”...

  • Page 112: Timer C

    R8C/11 Group 12.4 Timer (Timer C) 12.4 Timer C Timer C is a 16-bit timer. Figure 12.28 shows a block diagram of Timer C. Figure 12.29 shows a block diagram of CMP waveform generation unit. Figure 12.30 shows a block diagram of CMP waveform output unit.
  • Page 113 R8C/11 Group 12.4 Timer (Timer C) TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 TCC17 to TCC16 CMP output Latch (internal signal) Reverse Reset TCC15 to TCC14 Reverse TCC14 to TCC17: Bits in TCC1 register Figure 12.29 CMP Waveform Generation Unit P D 1 _ 0 T C O U T 6 = 0 C M P o u t p u t...
  • Page 114 R8C/11 Group 12.4 Timer (Timer C) T i m e r C r e g i s t e r ( b 1 5 ) ( b 8 ) S y m b o l A d d r e s s A f t e r r e s e t 0 0 9 1 - 0 0 9 0...
  • Page 115 R8C/11 Group 12.4 Timer (Timer C) T i m e r C c o n t r o l r e g i s t e r 1 Symbol Address After reset b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 TCC1 009B Bit symbol...

  • Page 116: Input Capture Mode

    R8C/11 Group 12.4 Timer (Timer C) 12.4.1 Input Capture Mode This mode uses an edge input to TC pin or the f clock as trigger to latch the timer value and RING128 generates an interrupt request. The TC input has a digital filter and this prevents an error caused by noise or so on from occurring.
  • Page 117 R8C/11 Group 12.4 Timer (Timer C) TCC00 bit in TCC0 register Measurement pulse pin input) TM0 register Rev.1.20 Jan 27, 2006 page 106 of 204 REJ09B0062-0120...

  • Page 118: Output Compare Mode

    R8C/11 Group 12.4 Timer (Timer C) 12.4.2 Output Compare Mode In this mode, an interrupt request is generated when the value of TC register matches the value of TM0 or TM1 register. Table 12.14 shows specifications in output compare mode. Figure 12.34 shows an operation example of output compare mode.
  • Page 119 R8C/11 Group 12.4 Timer (Timer C) M a t c h S e t v a l u e i n T M 1 r e g i s t e r C o u n t s t a r t M a t c h Match S e t v a l u e i n T M 0 r e g i s t e r...

  • Page 120: Chapter 13. Serial Interface

    R8C/11 Group 13. Serial Interface Rev.1.20 Jan 27, 2006 page 109 of 204 REJ09B0062-0120...

  • Page 121: Serial Interface

    R8C/11 Group 13. Serial Interface Clock synchronous type C l o c k PRYE=0 UART (7 bits) s y n c h r o n o u s U A R T i r e c e i v e r e g i s t e r P A R U A R T ( 7 b i t s ) UART (8 bits)
  • Page 122 R8C/11 Group 13. Serial Interface U A R T i t r a n s m i t b u f f e r r e g i s t e r ( i = 0 , 1 ) ( 1 , 2 ) S y m b o l A d d r e s s A f t e r r e s e t...
  • Page 123 R8C/11 Group 13. Serial Interface U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( i = 0 , 1 ) S y m b o l A d d r e s s A f t e r r e s e t...
  • Page 124 R8C/11 Group 13. Serial Interface U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( i = 0 , 1 ) Symbol Address After reset...

  • Page 125: Clock Synchronous Serial I/O Mode

    R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial I/O mode. Table 13.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
  • Page 126 R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function U0TB 0 to 7 Set transmission data U0RB 0 to 7 Reception data can be read Overrun error flag U0BRG 0 to 7...
  • Page 127 R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode • Example of transmit timing (when internal clock is selected) Transfer clock “1” U0C1 register TE bit Write data to U0TB register “0” U0C1 register “1” TI bit “0” Transferred from U0TB register to UART0 transmit register Stopped pulsing because the TE bit = 0 U0C0 register “1”...

  • Page 128: Polarity Select Function

    R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.1 Polarity Select Function Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. ( 1 ) W h e n t h e U 0 C 0 r e g i s t e r C K P O L b i t = 0 ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k ) C L K (1 )

  • Page 129: Continuous Receive Mode

    R8C/11 Group 13.1 Clock Synchronous Serial I/O Mode 13.1.3 Continuous Receive Mode Continuous receive mode is held by setting setting the U0RRM bit in the UCON register to “1” (en- ables continuous receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to “0”(data in the U0TB register).

  • Page 130: Clock Asynchronous Serial I/O (Uart) Mode

    R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode 13.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the registers and settings for UART mode.
  • Page 131 R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode Table 13.5 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate...
  • Page 132 R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock UiC1 register “1” TE bit Write data to UiTB register “0” “1” UiC1 register TI bit “0”...
  • Page 133 R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG output “1” UiC1 register RE bit “0” Stop bit Start bit RxDi Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock...

  • Page 134: Bit Rate

    R8C/11 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode 13.2.3 Bit Rate Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate. <UART Mode> • When selecting internal clock Setting value to the UiBRG register = –1 Bit Rate fj : Count source frequency of the UiBRG register (f1SIO, f8SIO and f32SIO)

  • Page 135: Chapter 14. A/D Converter

    R8C/11 Group 14. A/D Converter 14. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P0 to P0 and P1 to P1 . Therefore, when using these pins, make sure the corresponding port direction bits are set to “0”...
  • Page 136 R8C/11 Group 14. A/D Converter CKS1=1 φ CKS0=1 1 / 2 A/D conversion rate CKS1=0 C K S 0 = 0 selection VCUT=0 V C U T = 1 R e s i s t o r l a d d e r R E F S u c c e s s i v e c o n v e r s i o n r e g i s t e r ADCON0...
  • Page 137 R8C/11 Group 14. A/D Converter A D c o n t r o l r e g i s t e r 0 ( 1 ) S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b2 b 1 b 0 A D C O N 0 0 0 D 6...
  • Page 138 R8C/11 Group 14. A/D Converter A D c o n t r o l r e g i s t e r 2 (1 ) S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b 3 b 2 b1 b0 A D C O N 2 0 0 D 4...

  • Page 139: One-Shot Mode

    R8C/11 Group 14. One-shot mode 14.1 One-shot Mode In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 14.2 lists the specifications of one-shot mode. Figure 14.4 shows the ADCON0 and ADCON1 registers in one- shot mode.
  • Page 140 R8C/11 Group 14. One-shot mode A D c o n t r o l r e g i s t e r 0 (1 ) S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 A D C O N 0 0 0 D 6...

  • Page 141: Repeat Mode

    R8C/11 Group 14. Repeat mode 14.2 Repeat Mode In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 14.3 lists the specifications of repeat mode. Figure 14.5 shows the ADCON0 and ADCON1 registers in repeat mode.
  • Page 142 R8C/11 Group 14. Repeat mode A D c o n t r o l r e g i s t e r 0 (1 ) S y m b o l A d d r e s s A f t e r r e s e t b 7 b 6 b5 b 4 b3 b 2 b1 b 0 A D C O N 0 0 0 D 6...

  • Page 143: Sample And Hold

    R8C/11 Group 14.3 Sample and Hold/14.4 A/D conversion cycles 14.3 Sample and Hold If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 cycles for 8-bit resolution or 33 cycles for 10-bit resolution.
  • Page 144 R8C/11 Group Rev.1.20 Jan 27, 2006 page 133 of 204 REJ09B0062-0120...

  • Page 145: Inflow Current Bypass Circuit

    14.6 Inflow Current Bypass Circuit R8C/11 Group 14.6 Inflow Current Bypass Circuit Figure 14.9 shows the configuration of the inflow current bypass circuit, figure 14.10 shows the ex- ample of an inflow current bypass circuit where V or more is applied. Fixed to GND level Unselected channel To the internal logic...

  • Page 146: Output Impedance Of Sensor Under A/D Conversion

    14.7 Output Impedance of Sensor under A/D Conversion R8C/11 Group 14.7 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
  • Page 147 14.7 Output Impedance of Sensor under A/D Conversion R8C/11 Group Microcomputer S e n s o r e q u i v a l e n t c i r c u i t R ( 2 . 8 kΩ) C ( 6 p F ) N O T E : 1 .

  • Page 148: Chapter 15. Programmable I/O Ports

    R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports 15. 1 Description The programmable input/output ports (hereafter referred to as “I/O ports”) consist of 22 lines P0, P1, P3 to P3 , P3 , and P4 . Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines.
  • Page 149 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports Pull-up selection Direction regiister " 1 " Output D a t a b u s P o r t l a t c h ( N o t e 1 ) Analog input to P0 P u l l - u p s e l e c t i o n...
  • Page 150 R8C/11 Group 15. Programmable I/O Ports P u l l - u p s e l e c t i o n D i r e c t i o n r e g i s t e r P o r t l a t c h D a t a b u s ( N o t e 1 ) S e l e c t d r i v e c a p a c i t y...
  • Page 151 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports P u l l - u p s e l e c t i o n , P 1 D i r e c t i o n r e g i s t e r "...
  • Page 152 R8C/11 Group 15. Programmable I/O Ports P u l l - u p s e l e c t i o n D i r e c t i o n r e g i s t e r P o r t l a t c h D a t a b u s ( N o t e 1 ) D i g i t a l...

  • Page 153: Data Bus

    R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports D a t a b u s (Note 3) Clocked inverter (Note 2) O U T Data bus N O T E S : 1 . W h e n C M 0 5 = 1 , C M 1 0 = 1 , o r C M 1 3 = 0 , t h e c l o c k e d i n v e r t e r i s c u t o f f . 2 .
  • Page 154 R8C/11 Group 15. Programmable I/O Ports P o r t P i d i r e c t i o n r e g i s t e r ( i = 0 , 1 , 3 , 4 ) (1 , 2 , 3 ) S y m b o l A d d r e s s...
  • Page 155 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports P u l l - u p c o n t r o l r e g i s t e r 0 Symbol Address After reset PUR0 00FC 00XX0000 B i t s y m b o l B i t n a m e F u n c t i o n...

  • Page 156: Port Setting

    R8C/11 Group 15. Programmable I/O Ports 15.2 Port setting Table 15.1 to Table 15.23 list the port setting. Table 15.1 Port P0 Setting Register PUR0 ADCON0 UCON U1MR U1C0 CH2, CH1, CH0, SMD2, Function PD0_0 PU00 TXD1SEL ADGSEL0 SMD0 XXXX Input port (not pulled up) XXXX Input port (pulled up)
  • Page 157 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports Table 15.5 Port P0 Setting Register PUR0 ADCON0 Function PD0_4 PU01 CH2, CH1, CH0, ADGSEL0 XXXX Input port (not pulled up) XXXX Input port (pulled up) Setting value 0110 A/D input (AN XXXX Output port X: “0”...
  • Page 158 R8C/11 Group 15. Programmable I/O Ports _____ Table 15.10 Port P1 /CMP0 Setting Register PUR0 KIEN ADCON0 TCOUT CH2, CH1, CH0, Function PD1_1 PU02 DRR1 KI1EN TCOUT1 ADGSEL0 XXXX Input port (not pulled up) XXXX Input port (pulled up) _____ XXXX input 1011...
  • Page 159 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports Table 15.13 Port P1 Setting Register PUR0 U0MR U0C0 Function PD1_4 PU03 DRR4 SMD2, SMD0 Input port (not pulled up) Input port (pulled up) Output port Output port (High drive) output, CMOS output Setting value output, CMOS output (High drive)
  • Page 160 R8C/11 Group 15. Programmable I/O Ports _______ Table 15.16 Port P1 /INT /CNTR Setting Register PUR0 TXMR Function PD1_7 PU03 DRR5 TXMOD1, TXMOD0 Other than 01 Input port (not pulled up) Other than 01 Input port (pulled up) _______ Other than 01 CNTR /INT input...
  • Page 161 R8C/11 Group 15. Programmable I/O Ports 15. Programmable I/O Ports _______ Table 15.20 Port P3 /INT Setting Register PUR0 Function PD3_3 PU06 Input port (not pulled up) Input port (pulled up) Setting value /INT input Output port X: “0” or “1” Table 15.21 Port P3 Setting Register...

  • Page 162: Unassigned Pin Handling

    R8C/11 Group 15. Programmable I/O Ports 15.3 Unassigned Pin Handling Table 15.24 lists the handling of unassigned pins. Table 15.24 Unassigned Pin Handling P i n n a m e C o n n e c t i o n •...

  • Page 163: Chapter 16. Electrical Characteristics

    R8C/11 Group 16. Electrical Characteristics 16. Electrical Characteristics Table 16.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit Supply voltage -0.3 to 6.5 -0.3 to 6.5 Analog supply voltage Input voltage -0.3 to V +0.3 Output voltage -0.3 to V +0.3 Power dissipation Topr=25 C...
  • Page 164 R8C/11 Group 16. Electrical Characteristics Table 16.3 A/D Conversion Characteristics Standard S y m b o l P a r a m e t e r M e a s u r i n g c o n d i t i o n Unit M i n .
  • Page 165 R8C/11 Group 16. Electrical Characteristics Table 16.4 Flash Memory Version Electrical Characteristics Standard S y m b o l Measuring condition P a r a m e t e r U n i t M i n . T y p . M a x P r o g r a m / e r a s e e n d u r a n c e t i m e s...
  • Page 166 R8C/11 Group 16. Electrical Characteristics (1, 3) Table 16.6 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2 S t a n d a r d Symbol P a r a m e t e r Measuring condition Unit Min. Typ.
  • Page 167 R8C/11 Group 16. Electrical Characteristics S t a n d a r d S y m b o l P a r a m e t e r M e a s u r i n g c o n d i t i o n Unit M i n .
  • Page 168 R8C/11 Group 16. Electrical Characteristics Table 16.11 Electrical Characteristics (2) [Vcc=5V] S t a n d a r d S y m b o l P a r a m e t e r M e a s u r i n g c o n d i t i o n U n i t M i n .
  • Page 169 R8C/11 Group 16. Electrical Characteristics Timing requirements (Unless otherwise noted: V = 5V, V = 0V at Topr = 25 °C) [V =5V] Table 16.12 X input Standard Symbol Parameter Unit Min. Max. input cycle time – input HIGH pulse width –...
  • Page 170 R8C/11 Group 16. Electrical Characteristics = 5V c(CNTR0) WH(CNTR0) CNTR0 input WL(CNTR0) c(TCIN) WH(TCIN) TCIN input WL(TCIN) c(XIN) WH(XIN) input WL(XIN) c(CK) W(CKH) W(CKL) h(C-Q) d(C-Q) su(D-C) h(C-D) W(INL) W(INH) Figure 16.4 Vcc=5V timing diagram Rev.1.20 Jan 27, 2006 page 159 of 204 REJ09B0062-0120...
  • Page 171 R8C/11 Group 16. Electrical Characteristics Table 16.17 Electrical Characteristics (3) [Vcc=3V] S t a n d a r d M e a s u r i n g c o n d i t i o n S y m b o l P a r a m e t e r U n i t M i n .
  • Page 172 R8C/11 Group 16. Electrical Characteristics Table 16.18 Electrical Characteristics (4) [Vcc=3V] S t a n d a r d S y m b o l P a r a m e t e r Measuring condition U n i t Min.
  • Page 173 R8C/11 Group 16. Electrical Characteristics Timing requirements (Unless otherwise noted: V = 3V, V = 0V at Topr = 25 °C) [V =3V] Table 16.19 X input Standard Symbol Unit Parameter Min. Max. input cycle time – input HIGH pulse width –...
  • Page 174 R8C/11 Group 16. Electrical Characteristics = 3V c(CNTR0) WH(CNTR0) CNTR0 input WL(CNTR0) c(TCIN) WH(TCIN) TCIN input WL(TCIN) c(XIN) WH(XIN) input WL(XIN) c(CK) W(CKH) W(CKL) h(C-Q) d(C-Q) su(D-C) h(C-D) W(INL) W(INH) Figure 16.5 Vcc=3V timing diagram Rev.1.20 Jan 27, 2006 page 163 of 204 REJ09B0062-0120...

  • Page 175: Chapter 17. Flash Memory Version

    R8C/11 Group 17. Flash Memory Version 17. Flash Memory Version 17.1 Overview The flash memory version has two modes—CPU rewrite and standard serial I/O—in which its flash memory can be operated on. Table 17.1 outlines the performance of flash memory version (see “Table 1.1 Performance” for the items not listed on Table 17.1).

  • Page 176: Memory Map

    When setting the FMR16 bit to “0” (rewrite enabled), the Block 1 is rewritable (only for CPU rewrite mode). 2. This area is to store the boot program provided by Renesas Technology. Figure 17.1 Flash Memory Block Diagram Rev.1.20...

  • Page 177: Functions To Prevent Flash Memory From Rewriting

    R8C/11 Group 17.3 Functions To Prevent Flash Memory from Rewriting 17.3 Functions To Prevent Flash Memory from Rewriting 17.3 Functions To Prevent Flash Memory from Rewriting To prevent the flash memory from being read or rewritten easily, standard serial I/O mode has an ID code check function.

  • Page 178: Cpu Rewrite Mode

    R8C/11 Group 17.4 CPU Rewrite Mode 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on- board without having to use a ROM programmer, etc.

  • Page 179: Ew0 Mode

    R8C/11 Group 17.4 CPU Rewrite Mode 17.4 CPU Rewrite Mode 17.4.1 EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected.
  • Page 180 R8C/11 Group 17.4 CPU Rewrite Mode Figure 17.3 shows the FMR0 register. Figure 17.4 shows the FMR1 and FMR4 registers. • FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, eras- ing, or erase-suspend mode;...
  • Page 181 R8C/11 Group 17.4 CPU Rewrite Mode F l a s h m e m o r y c o n t r o l r e g i s t e r 0 b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 S y m b o l A d d r e s s A f t e r r e s e t...
  • Page 182 R8C/11 Group 17.4 CPU Rewrite Mode Flash memory control register 1 b7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 S y m b o l A d d r e s s A f t e r r e s e t F M R 1 0 1 B 5 0 1 0 0 X X 0 X...
  • Page 183 R8C/11 Group 17.4 CPU Rewrite Mode Figures 17.5 shows the timing on suspend operation. Erase Erase Erase Erase Starts Suspends Starts Ends During Erase During Erase FMR00 FMR46 Check that the FMR00 bit is Check the status, set to “0”, and that the erase and that the program operation has not ended.
  • Page 184 R8C/11 Group 17.4 CPU Rewrite Mode O n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) p r o g r a m T r a n s f e r o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) S e t t h e F M R 0 1 b i t b y w r i t i n g “...

  • Page 185: Software Commands

    R8C/11 Group 17.4 CPU Rewrite Mode 17.4.3 Software Commands Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.4 Software Commands First bus cycle Second bus cycle Command Data Data Mode Mode Address...
  • Page 186 R8C/11 Group 17.4 CPU Rewrite Mode • Program Command This command writes data to the flash memory in one byte units. Write ‘40 ’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start.
  • Page 187 R8C/11 Group 17.4 CPU Rewrite Mode • Block Erase Write ‘20 ’ in the first bus cycle and write ‘D0 ’ to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR00 bit in the FMR0 register to see if auto erasing has finished.
  • Page 188 R8C/11 Group 17.4 CPU Rewrite Mode < E W 0 M o d e > (1 , 2 ) S t a r t I n t e r r u p t F M R 4 0 = 1 F M R 4 0 = 1 W r i t e t h e c o m m a n d c o d e ‘...

  • Page 189: Status Register

    R8C/11 Group 17.4 CPU Rewrite Mode 17.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error. The status of the status register can be known by reading the FMR00, FMR06, and FMR07 bits in the FMR0 register.

  • Page 190: Full Status Check

    R8C/11 Group 17.4 CPU Rewrite Mode 17.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check).
  • Page 191 R8C/11 Group 17.4 CPU Rewrite Mode C o m m a n d s e q u e n c e e r r o r F u l l s t a t u s c h e c k E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( s e t t h e s e s t a t u s f l a g s t o 0 ) F M R 0 6 = 1...

  • Page 192: Standard Serial I/O Mode

    R8C/11 Group 17.5 Standard Serial I/O Mode 17.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for this microcomputer. Standard serial I/O mode has stan- dard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial.
  • Page 193 R8C/11 Group 17.5 Standard Serial I/O Mode Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode) P i n N a m e D e s c r i p t i o n I / O Apply the voltage guaranteed for Program and Erase to Vcc pin and P o w e r i n p u t 0V to Vss pin.
  • Page 194 R8C/11 Group 17.5 Standard Serial I/O Mode Rev.1.20 Jan 27, 2006 page 183 of 204 REJ09B0062-0120...
  • Page 195 R8C/11 Group 17.5 Standard Serial I/O Mode • Example of Circuit Application in the Standard Serial I/O Mode Figures 17.14 and 17.15 show examples of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.

  • Page 196: Chapter 18. On-Chip Debugger

    R8C/11 Group 18. On-chip Debugger 18. On-chip debugger The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip debugger. Next, here are some explanations for the respective functions.

  • Page 197: Chapter 19. Usage Notes

    R8C/11 Group 19. Usage Notes 19. Usage Notes 19.1 Stop Mode and Wait Mode 19.1.1 Stop Mode When entering stop mode, set the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled). The instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1”...

  • Page 198: Interrupts

    R8C/11 Group 19. Usage Notes 19.2 Interrupt 19.2.1 Reading Address 00000 Do not read the address 00000 by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000 in the interrupt sequence.

  • Page 199: Changing Interrupt Factor

    R8C/11 Group 19. Usage Notes 19.2.5 Changing Interrupt Factor The IR bit in the interrupt control register may be set to “1” (interrupt requested) when the interrupt factor is changed. When using an interrupt, set the IR bit to “0” (interrupt not request) after changing the interrupt factor.
  • Page 200 R8C/11 Group 19. Usage Notes...

  • Page 201: Clock Generation Circuit

    R8C/11 Group 19. Usage Notes 19.3 Clock Generation Circuit 19.3.1 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the main clock frequency is below 2MHz, set the OCD1 to OCD0 bits to “00 ” (oscillation stop detection function disabled). 19.3.2 Oscillation Circuit Constants Ask the maker of the oscillator to specify the best oscillation circuit constants on your system.

  • Page 202: Timers

    R8C/11 Group 19. Usage Notes 19.4 Timers 19.4.1 Timers X, Y and Z (1) Timers X, Y and Z stop counting after reset. Therefore, a value must be set to these timers and prescalers before starting counting. (2) Even if the prescalers and timers are read out simultaneously in 16-bit units, these registers are read byte-by-byte in the microcomputer.

  • Page 203: Serial Interface

    R8C/11 Group 19. Usage Notes 19.5 Serial Interface (1) When reading data from the UiRB (i=0,1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Be sure to read data in 16-bit unit. When the high-byte of the UiRB register is read, the PER and FER bits of the UiRB register and the RI bit of the UiC1 register are set to "0".

  • Page 204: A/D Converter

    R8C/11 Group 19. Usage Notes 19.6 A/D Converter (1) When writing to each bit but except bit 6 in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register, A/D conversion must be stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0”...

  • Page 205: Flash Memory Version

    R8C/11 Group 19. Usage Notes 19.7 Flash Memory Version 19.7.1 CPU Rewrite Mode Operation Speed Before entering CPU rewrite mode (EW0 mode, EW1 mode), select 5MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. Instructions Diabled Against Use The following instructions cannot be used in EW0 mode because the flash memory internal data is referenced: UND, INTO and BRK instructions.
  • Page 206 R8C/11 Group 19. Usage Notes Interrupt Table 19.1 list the Interrupt in EW0 Mode and Table 19.2 lists the Interrupt in EW1 Mode. Table 19.1 Interrupt in EW0 Mode Mode Status When maskable When watchdog timer, oscillation stop detection, and interrupt request is voltage detection interrupt request are acknowledged acknowledged...
  • Page 207 R8C/11 Group 19. Usage Notes Table 19.2 Interrupt in EW1 Mode Mode Status When maskable interrupt When watchdog timer, oscillation stop detection and request is acknowledged voltage detection interrupt request area acknowledged The auto-erasing is sus- Once an interrupt request is acknowledged, During auto- pended and the interrupt pro- the auto-programming or auto-erasing is forc-...

  • Page 208: Noise

    R8C/11 Group 19. Usage Notes 19.8 Noise (1) Bypass Capacitor between V and V Pins Insert a bypass capacitor (at least 0.1 µF) between V and V pins as the countermeasures against noise and latch-up. The connecting wires must be the shortest and widest possible. (2) Port Control Registers Data Read Error During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed.

  • Page 209: Chapter 20. Usage Notes For On-Chip Debugger

    R8C/11 Group 20. Usage Notes for On-chip Debugger 20. Usage notes for on-chip debugger When using the on-chip debugger to develop the R8C/11 group program and debug, pay the following attention. (1) Do not use P0 /TxD pin and P3 /TxD /RxD pin.

  • Page 210: Appendix 1 Package Dimensions

    R8C/11 Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP32-7x7-0.80 PLQP0032GB-A 32P6U-A 0.2g NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.

  • Page 211: Appendix Figure 2.2 Connecting Examples With M16C Flash Starter (M3A-0806)

    Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/11 Group Appendix 2. Connecting examples for serial writer and on-chip debugging emulator Appendix figure 2.1 shows connecting examples with USB Flash Writer and appendix figure 2.2 shows connecting examples with M16C Flash Starter. 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 3 kΩ...
  • Page 212 Appendix 2. Connecting Examples for Serial Writer and On-chip Debugging Emulator R8C/11 Group Appendix figure 2.3 shows connecting examples with emulator E7. 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 M O D E R 8 C / 1 1 V s s T x D...

  • Page 213: Appendix 3 Example Of Oscillation Evaluation Circuit

    R8C/11 Group Appendix 3. Package Dimensions Appendix 3. Example of Oscillation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. 24 23 22 21 20 19 18 17 0.1µF R8C/10 Group 1 2 3 4 5 6 7 8 Connect oscillation circuit...

  • Page 214: Register Index

    R8C/11 Group Register Index Register Index AD 127 OCD 32 ADCON0 126, 129, 131 ADCON1 126, 129, 131 ADCON2 127 P0 143 ADIC 53 AIER 67 P4 143 PD0 143 CM0 31 PD1 143 CM1 31 PD3 143 CMP0IC 53 PD4 143 CMP1IC 53 PM0 45...
  • Page 215 R8C/11 Group Register Index TM1 103 TX 72 TXIC 53 TXMR 62, 71, 73, 74, 75, 76, 78 TYIC 53 TYPR 81 TYSC 81 TYZMR 62, 80, 84, 86, 88, 92, 94, 96, 99 TYZOC 81, 89 TZIC 53 TZPR 89 TZSC 89 U0BRG 111 U0C0 112...
  • Page 216 R8C/11 Group Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 0.91 First edition issued Sep 08, 2003 0.92 Table 1.1 Interrupt : Revise 10 sources to 11 sources Nov 05, 2003 Add on Power Consumption Table 1.2 Delete ** Table 1.3 CNVss and MODE : Delete ( 5kΩ...
  • Page 217 R8C/11 Group Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 0.92 N Figure 10.9 Revise Compare 1 to Compare 0 and Compare 2 to Compare 1 ov 05, 2003 Figure 10.13 TYZMR, TYWC bit : Revise as Function varies depending on the operation mode Figure 10.14 Tcc1, Tcc 12 bit : Revise RO to RW Figure 11.1 is revised...
  • Page 218 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 0.92 Table 16.2 Delete NOTES 3 and 4 Nov 05, 2003 Table 16.3 Delete Tsamp Add Figure 16.1 Revise Table 16.4 Revise Table 16.5 Revise Table 16.6 Add Figure 16.2 Revise Figure 16.2 to Figure 16.3 Revise Figure 16.3, Add NOTES(4) Revise Table 16.7...
  • Page 219 R8C/11 Group Hardware Manual REVISION HISTORY Rev. Date Description Page Summary 0.92 Add Figure 16.5 Nov 05, 2003 Delete “Data” Retention on Table 17.1 Section 17.2 Add under the eighth line Add “Voltage detection” on Figure 17.2 Figure 17.4 FMR1, bit 6 : Delete “When read, its content is indeterminate” Revise RO to Section 17.5 Add sentences Table 17.7, P46/XIN and P47/XOUT, revise sentences...
  • Page 220 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.00 Sep 17,2004 Figure 5.11 revised Figure 5.12 revised Line 10 in 5.4.1 revised Line 5 in 5.4.2 revised One sentence in 5.4.2 deleted Table 5.3 revised Figure 6.1 revised Figure 6.2 revised (CM0 and CM1) Figure 6.3 revised Figure 6.4 revised (HR0)
  • Page 221 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.00 Sep 17,2004 Figure numbers in 15.1.1, 15.1.2, 15.1.3 and 15.1.4 revised Figure 15.1 revised (P1 to P1 Table 15.1 revised Table 16.2 revised Table 16.3 revised Table 16.4 revised; Table 16.5 revised Table 16.6, 16.7 and 16.8 revised;...
  • Page 222 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.10 Apr.27.2005 6.5 partly deleted Table 6.4 partly deleted 6.5.1 partly revised Figure 11.2 partly revised Figure 12.9 partly revised Table 12.11 partly revised Table 12.12 partly revised Figure12.31 partly revised Table 13.6 partly revised 13.2.3 Bit Rate added Figure 14.6 partly revised...
  • Page 223 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.20 Jan.27.2006 Table 4.3 SFR Information(3); : “Prescaler Y” → “Prescaler Y Register” 0081 : “Timer Y Secondary” → “Timer Y Secondary Register” 0082 : “Timer Y Primary” → “Timer Y Primary Register” 0083 : “Prescaler Z”...
  • Page 224 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.20 Jan.27.2006 Table 15.9 Port P1 /CMP0 Setting; Setting value: Output port, P1 deleted _____ Table 15.10 Port P1 /CMP0 Setting; Setting value: Output port, P1 deleted _____ Table 15.11 Port P1 /CMP0 Setting;...
  • Page 225 REVISION HISTORY R8C/11 Group Hardware Manual Rev. Date Description Page Summary 1.20 Jan.27.2006 19.1.1 Stop Mode; “Use the next program to enter stop mode.” added “• Example of entering stop mode” →“• Program of entering stop mode” “Program Example” deleted 19.3.1 Oscillation Stop Detection Function “Since the oscillation stop ...
  • Page 226 RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL R8C/11 Group Publication Data : Rev.0.93 Feb 18, 2004 Rev.1.20 Jan 27, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
  • Page 227 R8C/11 Group Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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