Renesas M16C/50 Series User Manual page 398

M16C/5L Group, M16C/56 Group
18.2.11 Base Timer Reset Register (G1BTRR)
Base Timer Reset Register
b15 b8
(b7) (b0) b7
Write to the G1BTRR register in 16-bit units. The value written to this register is reflected to the internal
circuit when the clock is synchronized with the base timer count source (fBT1).
While the RST4 bit in the G1BCR0 register is 1, rewrite the G1BTRR register when the BTS bit in the
G1BCR1 register is 0 (base timer reset).
18.2.12 Count Source Divide Register (G1DV)
Count Source Divide Register
b7
Rewrite the G1DV register when bits BCK1 and BCK0 in the G1BCR0 register are 00b (clock stopped).
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0 Symbol
G1BTRR
When the RST4 bit in the G1BCR0 register is 1, the base timer is
reset by matching the G1BTRR register value and base timer value.
Symbol
b0
G1DV
Divide f1TIMS, f2TIMS, or the two-phase input pulse clock by (n + 1)
to generate fBT1.
n: G1DV setting value
Address
02E9h to 02E8h
Function
Address
02EAh
Function
18. Timer S
Reset Value
XXXXh
Setting Range RW
0001h to FFFFh RW
Reset Value
00h
Setting Range RW
00h to FFh RW
Page 361 of 803