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M16C/5L Group, M16C/56 Group
(1) SWC bit function
SDA2 (master)
SCL2 (master)
SDA2 (slave)
SCL2 (slave)
(2) SWC9 bit function
SDA2 (master)
SCL2 (master)
SDA2 (slave)
SCL2 (slave)
Figure 21.19 Inserting Wait-States Using Bits SWC and SWC9
The CSC bit in the U2SMR2 register synchronizes an internally generated clock with the clock applied
to the SCL2 pin. For example, if a wait-state is inserted from other devices, the two clocks are not
synchronized. While the CSC bit is 1 (clock synchronization enabled) and the internal clock is held high,
when a high at the SCL2 pin changes to low, the internal clock becomes low in order to reload the
U2BRG register value and resume counting. While the SCL2 pin is held low, when the internal clock
changes from low to high, the count is stopped until the SCL2 pin becomes high. That is, the UART2
transmit/receive clock is the logical AND of the internal clock and SCL2. The synchronized period starts
from one clock prior to an internally generated clock and ends when the ninth clock is completed. The
CSC bit can be set to 1 only when the CKDIR bit in the U2MR register is set to 0 (internal clock
selected).
The SCLHI bit in the U2SMR4 register is used to leave the SCL2 pin open when another master
generates a stop condition while the master is performing a transmit/receive operation. While the
SCLHI bit is set to 1 (output stopped), the SCL2 pin is open (the pin is high-impedance) when a stop
condition is detected and the clock output is stopped.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
1
2
3
4
Address bit comparison, acknowledge generation
1
2
3
4
21. Serial Interface UARTi (i = 0 to 4)
5
6
7
8
Clock line is
held low
5
6
7
8
Acknowledge check
Clock line is
held low
9
A/A
Clock line is
released
(SWC = 0)
A/A
9
Clock line is
released
(SWC9 = 0)
Page 477 of 803
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