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M16C/5L Group, M16C/56 Group
6.2.2
Reset Source Determine Register (RSTFR)
Reset Source Determine Register
b7
b6 b5 b4
b3
b2
b1
0
0
Table 6.5
RSTFR Register Reset Value
Reset
Hardware reset
Power-on reset
Voltage monitor 0 reset
Voltage monitor 2 reset
Oscillator stop detect reset
Watchdog timer reset
Software reset
HWR (Hardware Reset Detect Flag) (b1)
When setting the LVDAS bit in the OFS1 address to 0 (voltage detector 0 reset is enabled after
resetting the hardware), or the voltage monitor 0 reset is enabled by a program after reset, the HWR bit
after the hardware reset is undefined.
OSDR (Oscillator stop detect reset detect flag) (b6)
The OSDR bit also changes when following condition is met:
Conditions to become 0:
•
Power-on
•
Setting this bit to 0
This bit will not become 1 even when written to 1.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
0
Symbol
RSTFR
Bit Name
Bit Symbol
—
Reserved bit
(b0)
HWR
Hardware reset detection flag
SWR
Software reset detection flag
Watchdog timer reset detection
WDR
flag
—
Reserved bit
(b4)
Voltage monitor 2 reset
LVD2R
detection flag
Oscillator stop detect reset
OSDR
detect flag
—
Reserved bit
(b7)
OSDR
No change
Address
0018h
If necessary, set to 0. The read value is
undefined.
0: Not detected
1: Detected
0: Not detected
1: Detected
0: Not detected
1: Detected
If necessary, set to 0. The read value is
undefined.
0: Not detected
1: Detected
0: Not detected
1: Detected
If necessary, set to 0. The read value is
undefined.
Bits in the RSTFR Register
LVD2R
0
0
0
0
0
0
1
1
0
0
0
0
0
Reset Value
See Table 6.5.
Function
WDR
SWR
0
0
0
0
0
0
0
0
0
0
1
0
0
1
Page 63 of 803
6. Resets
RW
RW
RO
RO
RO
RW
RO
RW
RW
HWR
1
0
0
0
0
0
0
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