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M16C/5L Group, M16C/56 Group
Table 21.7
Registers Used and Settings in Clock Synchronous Serial I/O Mode
Register
OCOSEL0
UCLKSEL0
OCOSEL1
PCLKR
UiTB
UiRB
8, 11, 13 to 15
UiBRG
SMD2 to SMD0
UiMR
CLK1 to CLK0
UiC0
CKPOL
UFORM
UiC1
(2)
U2SMR
(2)
U2SMR2
(2)
U2SMR3
(2)
U2SMR4
i = 0 to 4
Notes:
1.
This table does not describe a procedure.
2.
In case of UART2
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Bits
Select clock prior to division for UART0 to UART2.
Select clock prior to division for UART3 to UART4.
PCLK1
Select the count source for the UiBRG register.
0 to 7
Set transmission data.
8
- (does not need to be set) If necessary, set to 0.
0 to 7
Reception data can be read.
When read, the read value is undefined.
OER
Overrun error flag
0 to 7
Set bit rate.
Set to 001b.
CKDIR
Select internal clock or external clock.
4 to 6
Set to 0.
IOPOL
Set to 0.
Select the count source for the UiBRG register.
If CTS or RTS is used, select which function to use.
CRS
TXEPT
Transmit register empty flag
Enable or disable the CTS or RTS function. Set this bit to 1 (disabled) when using
CRD
UART4.
NCH
Select TXDi pin output mode.
Select the transmit/receive clock polarity.
Select LSB first or MSB first.
TE
Set to 1 to enable transmission/reception.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
UiIRS
Select source of UARTi transmit interrupt.
UiRRM
Set to 1 to use continuous receive mode.
UiLCH
Set to 1 to use inverted data logic.
UiERE
Set to 0.
0 to 7
Set to 0.
0 to 7
Set to 0.
0 to 2
Set to 0.
NODC
Select clock output mode.
4 to 7
Set to 0.
0 to 7
Set to 0.
21. Serial Interface UARTi (i = 0 to 4)
(1)
Function
Page 452 of 803
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