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M16C/5L Group, M16C/56 Group
Table 9.2
Clocks in Normal Operating Mode
Mode
Main clock
High-speed
mode
divided by 1
Main clock
Medium-speed
mode
divided by n
PLL clock
PLL operating
mode
divided by n
fOCO-F divided
40 MHz on-chip
oscillator mode
by n
fOCO-S divided
125 kHz on-chip
oscillator mode
by n
125 kHz on-chip
fOCO-S divided
oscillator low
by n
power mode
Low-speed
fC
mode
Low power
fC
mode
CM11
: Bit in the CM1 register
CM21
: Bit in the CM2 register
FRA01 : Bit in the FRA0 register
Notes:
1. Select by setting the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register.
2. The peripheral clock is enabled when each clock is supplied. Refer to 8. "Clock Generator" for the
clock supply method.
Table 9.3
Clock-Related Bit Setting and Modes
Mode
High-speed mode,
medium-speed mode
PLL operating mode
40 MHz on-chip oscillator mode
125 kHz on-chip oscillator mode
125 kHz on-chip oscillator low
power mode
Low-speed mode
Low power mode
Note:
1. Both or either the main clock and fOCO-F are oscillated.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
CPU Clock
(1)
Main clock divided by 1
(1)
PLL clock divided by 1
(1)
fOCO-F divided by 1
(1)
fOCO-S divided by 1
(1)
fOCO-S divided by 1
(1)
Any of the following:
Main clock divided by 1 (when the CM21
is 0 and the CM11 is 0)
PLL clock divided by 1 (when the CM21 is
0 and the CM11 is 1)
fOCO-F divided by 1 (when the CM21 is 1
and the FRA01 is 1)
fOCO-S divided by 1 (when the CM21 is 1
and the FRA01 is 0)
fOCO-S divided by 1
(when the CM21 is 1 and the FRA01 is 0)
CM2 Register CM1 Register
CM21
0
0
1
1
1
−
−
Peripheral Clocks
f1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
CM0 Register
CM14 CM11 CM07 CM05 CM04 FRA01 FRA00
−
0
0
−
1
0
−
0
0
0
0
0
0
0
0
−
0
1
−
0
1
9. Power Control
(2)
fOCO-F
fC, fC32
fOCO-S
fOCO40M
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Enabled
Enabled
Enabled
Disabled
FRA0 Register
−
−
0
−
−
0
−
−
1
−
(1)
0
0
−
1
0
−
(1)
1
0
−
1
1
−
Page 124 of 803
−
−
1
(1)
1
0
(1)
1
0
: 0 or 1
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