Advertisement
M16C/5L Group, M16C/56 Group
17.5
Notes on Three-Phase Motor Control Timer Function
17.5.1
Timer A and Timer B
Refer to 15.5 "Notes on Timer A" and 16.5 "Notes on Timer B".
Influence of SD
17.5.2
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V/RXD1, P7_3/ CTS2 / RTS2 /TA1IN/ V /TXD1, P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/U/TSUDA, P8_1/TA4IN/ U /TSUDB
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
17. Three-Phase Motor Control Timer Function
Page 343 of 803
Advertisement
