Download Print this page

Renesas M16C/50 Series User Manual page 543

Advertisement

M16C/5L Group, M16C/56 Group
Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches)
The TOF bit in the S4D0 register: 0 (timeout not detected)
ALS (Data format select bit) (b4)
The ALS bit is enabled in slave mode. When the ALS bit is 0 (addressing format), the slave address
match detection is performed.
When a slave address stored to bits SAD6 to SAD0 in the S0Di register (i = 0 to 2) is compared and
matched with the calling address by a master, or when a general call address is received, the IR bit in
the IICIC register becomes 1 (interrupt requested).
When the ALS bit is 1 (free data format), the slave address match detection is not performed.
Therefore, the IR bit in the IICIC register becomes 1 (interrupt requested), regardless of the calling
address by a master.
2
IHR (I
C-bus interface reset bit) (b6)
The IHR bit resets the I
bit in the S1D0 register is 1 (I
interface becomes as follows:
S10 register
ADR0 bit: 0 (general call not detected)
AAS bit: 0 (slave address not matched)
AL bit: 0 (arbitration lost not detected)
PIN bit: 1 (No I
BB bit: 0 (bus free)
TRX bit: 0 (receive mode)
MST bit: 0 (slave mode)
Bits AAS2 to AAS0 in the S11 register: 0 (slave address not matches)
TOF bit in the S4D0 register: 0 (timeout not detected)
When the IHR bit is set to 1, the I
a maximum of 2.5 fVIIC cycles to complete the reset sequence.
Figure 22.3 shows the I
IHR bit in the S1D0 register
2
I
C interface reset signal
2
Figure 22.3
I
C Interface Reset Timing
2
TISS (I
C-bus interface pin input level select bit) (b7)
Set the TISS bit to select the input level of the SCLMM pin and SDAMM pin for the I
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C interface if there is an anomaly during transmission/reception. When the ES0
2
C interface enabled) and then the IHR bit is set to 1 (reset), the I
2
C-bus interrupt request)
2
C interface is reset and the IHR bit becomes 0 automatically. It takes
2
C Interface Reset Timing.
Set to 1 by a program
2.5 fVIIC cycles
2
22. Multi-master I
C-bus Interface
2
C interface.
Page 506 of 803
2
C

Advertisement

loading