Renesas M16C/50 Series User Manual page 563

M16C/5L Group, M16C/56 Group
The start condition generation timing depends on the modes - standard clock mode or fast-mode.
Figure 22.7 shows the Start Condition Generation Timing.
Table 22.12 lists the Setup/Hold Time for Generating a Start/Stop Condition.
Write signal to the S00 register
BB bit in the S10 register
Figure 22.7 Start Condition Generation Timing
Table 22.12 Setup/Hold Time for Generating a Start/Stop Condition
Item STSPSEL Bit
0 (short mode)
Setup time
1 (long mode)
0 (short mode)
Hold time
1 (long mode)
BB bit
set/reset
time
-: 0 or 1
STSPSEL: Bit in the S2D0 register
SSC value: Value of bits SSC4 to SSC0 in the S2D0 register
Note:
1. Example value when bits SSC4 to SSC0 are 11000b.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
SCLMM
SDAMM
Standard Clock Mode
fVIIC cycles
20
52
20
52
SSC value 1
–
-
------------------------------------ -
2
Setup Hold
Setup
BB bit
fVIIC = 4 MHz
5.0 μ s
13.0 μ s
5.0 μ s
13.0 μ s
3.375 μ s
(1)
2
+
2
22. Multi-master I C-bus Interface
Fast-mode
fVIIC cycles fVIIC = 4 MHz
2.5 μ s
10
6.5 μ s
26
2.5 μ s
10
6.5 μ s
26
0.875 μ s
3.5
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