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M16C/5L Group, M16C/56 Group
21.2.10 UART2 Special Mode Register 3 (U2SMR3)
UART2 Special Mode Register 3
b7 b6 b5 b4
b3
b2
b1
NODC (Clock output select bit) (b3)
This function is used to set P-channel transistor of the CMOS output buffer always off, but not to
change the CLK2 pin to open drain output completely.
Refer to the electrical characteristics for the input voltage range.
DL2-DL0 (SDA2 digital delay setup bit) (b7-b5)
Bits DL2 to DL0 are used to generate a digital delay in SDA2 output in I
set these bits to 000b (no delay).
The delay length varies with the load on pins SCL2 and SDA2. Also, when using an external clock, the
delay length increases by about 100 ns.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
U2SMR3
Bit Symbol
Bit Name
—
No register bit. If necessary, set to 0. The read value is undefined.
(b0)
Clock phase set bit
CKPH
—
No register bit. If necessary, set to 0. The read value is undefined.
(b2)
NODC
Clock output select bit
—
No register bit. If necessary, set to 0. The read value is undefined.
(b4)
DL0
SDA2 digital delay
DL1
setup bit
DL2
21. Serial Interface UARTi (i = 0 to 4)
Address
0265h
Function
0 : No clock delay
1 : With clock delay
0 : CLK2 is CMOS output
1 : CLK2 is N-channel open drain output
b7 b6 b5
0 0 0 : No delay
0 0 1 : 1 to 2 cycles of U2BRG count source
0 1 0 : 2 to 3 cycles of U2BRG count source
0 1 1 : 3 to 4 cycles of U2BRG count source
1 0 0 : 4 to 5 cycles of U2BRG count source
1 0 1 : 5 to 6 cycles of U2BRG count source
1 1 0 : 6 to 7 cycles of U2BRG count source
1 1 1 : 7 to 8 cycles of U2BRG count source
2
C mode. Except in I
Reset Value
000X 0X0Xb
RW
—
RW
—
RW
—
RW
RW
RW
2
C mode,
Page 446 of 803
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