Renesas M16C/50 Series User Manual page 136

M16C/5L Group, M16C/56 Group
8.2.4 Peripheral Clock Select Register (PCLKR)
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0 0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
PCLK5 (Clock output function extension bit) (b5)
Output from the CLKOUT pin is selectable. When the PCLK5 bit is 1, set bits CM01 and CM00 to 00b.
See Table 8.4 "CLKOUT Pin Functions".
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Symbol
b0
PCLKR
Bit Symbol Bit Name
Timers A, B, S, multi-master I
interface clock select bit
PCLK0 (clock source for timers A , B, S,
dead time timer, and multi-master
2
I C-bus interface)
SI/O clock select bit
PCLK1 (clock source for UART0 to
UART4)
—
Reserved bits
(b4-b2)
PCLK5 Clock output function extension bit
—
Reserved bits
(b7-b6)
Address
0012h
Function
2
C-bus
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
0: f2SIO
1: f1SIO
Set to 0.
0: Selected by setting bits CM01 and CM00 in
the CM0 register
1: Outputs f1
Set to 0.
8. Clock Generator
Reset Value
00000011b
RW
RW
RW
RW
RW
RW
Page 99 of 803