Renesas M16C/50 Series User Manual page 632

M16C/5L Group, M16C/56 Group
23.1.25 CAN0 Test Control Register (C0TCR)
CAN0 Test Control Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0 0
Note:
1. Write to the C0TCR register only in CAN halt mode.
Figure 23.30 C0TCR Register
23.1.25.1 TSTE Bit
When the TSTE bit is set to 0, CAN test mode is disabled.
When this bit is set to 1, CAN test mode is enabled.
23.1.25.2 TSTM Bit
The TSTM bit selects the CAN test mode.
The details of each CAN test mode is described below.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
(1)
b0
Symbol
C0TCR
Bit Symbol
TSTE CAN Test Mode Enable Bit
TSTM CAN Test Mode Select Bit
—
Reserved
(b7-b3)
Address
D7D8h
Bit Name
0: CAN test mode disabled
1: CAN test mode enabled
b2 b1
0 0 : Other than CAN test mode
0 1 : Listen-only mode
1 0 : Self-test mode 0 (external loop back)
1 1 : Self-test mode 1 (internal loop back)
Set to 0.
23. CAN Module
Reset Value
00h
Function RW
RW
RW
RW
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