Renesas M16C/50 Series User Manual page 624

M16C/5L Group, M16C/56 Group
23.1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR)
CAN0 Error Interrupt Factor Judge Register
b7 b6 b5 b4 b3 b2 b1
Note:
1. When writing 0 to these bits by a program, use the MOV instruction to ensure that only the specified bit is
set to 0 and the other bits are set to 1. Writing 1 has no effect to these bit values.
Figure 23.25 C0EIFR Register
If an event corresponding to each bit occurs, the corresponding bit in the C0EIFR register is set to 1
regardless of the setting of the C0EIER register.
To set each bit to 0, write 0 by a program. If the set timing occurs simultaneously with the clear timing by
the program, the bit becomes 1.
23.1.20.1 BEIF Bit
The BEIF bit is set to 1 when a bus error is detected.
23.1.20.2 EWIF Bit
The EWIF bit is set to 1 when the value of the receive error counter (REC) or transmit error counter
(TEC) exceeds 95.
This bit is set to 1 only when the REC or TEC initially exceeds 95. Thus, if 0 is written to the EWIF bit by
a program while the REC or TEC remains greater than 95, this bit is not set to 1 until the REC and the
TEC go below 95 and then exceed 95 again.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
C0EIFR
Bit Symbol
Bus Error
BEIF
Detect Flag
Error Warning
EWIF
Detect Flag
Error Passive
EPIF
Detect Flag
Bus-Off Entry
BOEIF
Detect Flag
Bus-Off Recovery
BORIF
Detect Flag
Receive Overrun
ORIF
Detect Flag
Overload Frame
OLIF Transmission
Detect Flag
BLIF Bus Lock Detect Flag
(1)
Address
D7CDh
Bit Name
0: No bus error detected
1: Bus error detected
0: No error warning detected
1: Error warning detected
0: No error passive detected
1: Error passive detected
0: No bus-off entry detected
1: Bus-off entry detected
0: No bus-off recovery detected
1: Bus-off recovery detected
0: No receive overrun detected
1: Receive overrun detected
0: No overload frame transmission
detected
1: Overload frame transmission
detected
0: No bus lock detected
1: Bus lock detected
23. CAN Module
Reset Value
00h
Function RW
RW
RW
RW
RW
RW
RW
RW
RW
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