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M16C/5L Group, M16C/56 Group
22.3.3
Generating a Stop Condition
Use the following procedure when the ES0 bit in the S1D0 register is 1 (I
(1) Write C0h to the S10 register.
2
The I
C interface enters the stop condition standby state and the SDAMM pin is driven low.
(2) Write dummy data to the S00 register.
A stop condition is generated.
The stop condition generation timing depends on the modes - standard clock mode or fast-mode.
Figure 22.8 shows the Stop Condition Generation Timing. See Table 22.12 "Setup/Hold Time for
Generating a Start/Stop Condition" for setup/hold time.
Write signal to the S00 register
BB bit in the S10 register
Figure 22.8
Stop Condition Generation Timing
Do not write to the S10 register or S00 register until the BB bit in the S10 register becomes 0 (bus free)
after the instructions to generate a stop condition (refer to above (2)) are executed.
If the SCLMM pin input signal becomes low until the BB bit in the S10 register becomes 0 (bus free)
from the instruction to generate a stop condition is executed and the SCLMM pin becomes high-level,
the internal SCL output becomes low. In this case, perform one of the steps below to stop the low signal
output from the SCLMM pin (release the SCLMM pin).
•
Generate a stop condition (perform steps (1) and (2) above).
•
Set the ES0 bit in the S1D0 register to 0 (I
•
Write 1 to the IHR bit (I
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
SCLMM
SDAMM
2
C interface disabled).
2
C interface reset).
22. Multi-master I
2
C interface enabled).
Setup
Hold
Setup
BB bit
2
C-bus Interface
Page 527 of 803
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