Advertisement
28.14.1
Register Access ............................................................................................................... 783
28.14.2
Changing the G1IR Register ........................................................................................... 783
28.14.3
Changing Registers ICOCiIC (i = 0, 1) ............................................................................ 785
28.14.4
Output Waveform During the Base Timer Reset with the BTS bit ................................... 785
28.14.5
OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 register ................ 785
28.14.6
Interrupt Request When Selecting Time Measurement Function .................................... 785
28.15
Notes on Task Monitor Timer .................................................................................................... 786
28.15.1
Register Settings ............................................................................................................. 786
28.15.2
Reading the Timer ........................................................................................................... 786
28.16
Notes on Real-Time Clock ........................................................................................................ 787
28.16.1
Starting and Stopping the Count ...................................................................................... 787
28.16.2
Register Settings (Time Data, etc.) .................................................................................. 787
28.16.3
Register Settings (Compare Data) .................................................................................. 787
28.16.4
Time Reading Procedure in Real-Time Clock Mode ....................................................... 788
28.17
Notes on Serial Interface UARTi (i = 0 to 4) ............................................................................. 789
28.17.1
Common Notes on Multiple Modes ................................................................................. 789
28.17.2
Clock Synchronous Serial I/O Mode ................................................................................ 789
28.17.3
Special Mode 1 (I
28.17.4
Special Mode 4 (SIM Mode) ............................................................................................ 792
28.18
Notes on Multi-master I
28.18.1
Limitation on CPU Clock .................................................................................................. 793
28.18.2
Register Access ............................................................................................................... 793
28.19
Notes on CAN Module .............................................................................................................. 794
28.20
Notes on A/D Converter............................................................................................................ 795
28.20.1
Analog Input Pin .............................................................................................................. 795
28.20.2
Pin Configuration ............................................................................................................. 795
28.20.3
Register Access .............................................................................................................. 795
28.20.4
A/D Conversion Start ....................................................................................................... 796
28.20.5
A/D Operation Mode Change .......................................................................................... 796
28.20.6
State When Forcibly Terminated ...................................................................................... 796
28.20.7
A/D Open-Circuit Detection Assist Function .................................................................... 796
28.20.8
Detecting Completion of A/D Conversion ........................................................................ 796
φ AD .................................................................................................................................. 796
28.20.9
28.21
Notes on Flash Memory........................................................................................................... 797
28.21.1
OFS1 Address, OFS2 Address, and ID Code Storage Address ...................................... 797
28.21.2
Reading Data Flash ......................................................................................................... 797
28.21.3
CPU Rewrite Mode .......................................................................................................... 798
28.21.4
User Boot ......................................................................................................................... 800
REGISTER INDEX .......................................................................................................... 801
2
C Mode) ............................................................................................. 790
2
C-bus Interface .................................................................................. 793
A- 18
Advertisement
