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M16C/5L Group, M16C/56 Group
23.1.14.1 RSTST Bit
The RSTST bit is set to 1 when the CAN module is in CAN reset mode.
This bit is set to 0 when the CAN module is not in CAN reset mode.
Even when the state is changed from CAN reset mode to CAN sleep mode, the RSTST bit remains 1.
23.1.14.2 HLTST Bit
The HLTST bit is set to 1 when the CAN module is in CAN halt mode.
This bit is set to 0 when the CAN module is not in CAN halt mode.
Even when the state is changed from CAN halt mode to CAN sleep mode, the HLTST bit remains 1.
23.1.14.3 SLPST Bit
The SLPST bit is set to 1 when the CAN module is in CAN sleep mode.
This bit is set to 0 when the CAN module is not in CAN sleep mode.
23.1.14.4 EPST Bit
The EPST bit is set to 1 when the value of the C0TECR or C0RECR register exceeds 127 and the CAN
module is in error-passive state (128 ≤ TEC < 256 or 128 ≤ REC < 256). This bit is set to 0 when the
CAN module is not in error-passive state.
TEC indicates the value of the transmit error counter (C0TECR register) and REC indicates the value of
the receive error counter (C0RECR register).
23.1.14.5 BOST Bit
The BOST bit is set to 1 when the value of the C0TECR register exceeds 255 and the CAN module is in
bus-off state (TEC ≥ 256). This bit is set to 0 when the CAN module is not in bus-off state.
23.1.14.6 TRMST Bit
The TRMST bit is set to 1 when the CAN module performs as a transmitter node or is in bus-off state.
This bit is set to 0 when the CAN module performs as a receiver node or is in bus-idle state.
23.1.14.7 RECST Bit
The RECST bit is set to 1 when the CAN module performs as a receiver node.
This bit is set to 0 when the CAN module performs as a transmitter node or is in bus-idle state.
23.1.14.8 NDST Bit
The NDST bit is set to 1 when at least one NEWDATA bit in the C0MCTLj register (j = 0 to 31) is 1
regardless of the value of the C0MIER register.
The NDST bit is set to 0 when all NEWDATA bits are 0.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
23. CAN Module
Page 578 of 803
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