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M16C/5L Group, M16C/56 Group
12.4
Software Interrupts
A software interrupt occurs when executing instructions. Software interrupts are non-maskable interrupts.
12.4.1
Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
12.4.2
Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set
to 1 (the operation resulted in an overflow). The following are instructions whose O flag changes by an
arithmetic operation:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB
12.4.3
BRK Interrupt
A BRK interrupt occurs when the BRK instruction is executed.
12.4.4
INT Instruction Interrupt
An INT instruction interrupt occurs when the INT instruction is executed. Software interrupt numbers 0
to 63 can be specified for the INT instruction. Because software interrupt numbers 4, 8 to 31, 41, 42,
and 47 to 63 are assigned to peripheral function interrupts, the same interrupt routine used for
peripheral function interrupts can be executed by executing the INT instruction.
For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and
is cleared to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does
not change state during instruction execution, and the SP selected at the time is used.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
12. Interrupts
Page 180 of 803
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