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M16C/5L Group, M16C/56 Group
26.8.7.1
Full Status Check
If an error occurs, bits FMR06 and FMR07 in the FMR0 register become 1, indicating the occurrence
of an error. Therefore, the execution results can be confirmed by checking these status bits (full
status check).
Table 26.19
Errors and FMR0 Register States
FMR00 Register
FMR07 bit FMR06 bit
1
1
1
0
0
1
Notes:
1.
When writing xxFFh in the second bus cycle of the command, the flash memory becomes the
state before executing the command, and the command code written in the first bus cycle is
cancelled.
2.
When the FMR02 bit is 1 (lock bit disabled), no error occurs even under the conditions above.
Figure 26.24 Full Status Check
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Error
• Command is written incorrectly.
• Data other than xxD0h and xxFFh is written in the second
Command
bus cycle of the lock bit program, block erase, block
sequence error
blank check, or read lock bit status command.
• The block erase command is executed on a locked block.
(2)
• The block erase command is executed on an unlocked
Erase error
block, but the auto-erase operation is not completed as
expected.
• The block blank check command is executed, and the
check result is not blank.
• The program command is executed on a locked block.
• The program command is executed on an unlocked
block, but the auto-program operation is not completed
Program error
as expected.
• The lock bit program command is executed, but the lock
bit is not written as expected.
Full status check
FMR06 = 1
and
FMR07 = 1?
No
FMR07 = 0?
Yes
FMR06 = 0?
Full status check
completed
FMR07, FMR06: Bits in the FMR0 register
Error Occurrence Conditions
Yes
Command sequence
error
No
Erase error
No
Program error
26. Flash Memory
(1)
(2)
Page 689 of 803
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