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REVISION HISTORY
Rev.
Date
Page
1.10 Sep. 01, 2011
748
K-Version, V
749
750
757
Usage Notes
Chap. 28. 28.1 OFS1 Address and ID Code Storage: Deleted since same description is in the Flash chapter.
Chap. 28. 28.21.2 φ AD Frequency: Deleted.
Chap. 28. 28.22.1 Functions to Prevent Flash Memory from Being Rewritten: Deleted.
760
762
766
767
767
767
768
768
769
776
780
782
783
783
784
785
785
785
789
789, 790
791-792
792
M16C/5L, M16C/56 Group User's Manual: Hardware
2
Figure 27.37 Multi-master I
C-bus: Changed t
= 3 V
CC
Table 27.73 Electrical Characteristics (1):
Changed the maximum value of V
"1.8".
Table 27.74 Electrical Characteristics (2):
• Changed the typical value of 125 kHz on-chip oscillator mode from "160".
• Changed the typical value of low power mode from "450".
2
Figure 27.46 Multi-master I
C-bus: Changed t
Table 28.2 Read-Modify-Write Instructions: Added.
Figure 28.2 SVCC Timing: Revised.
28.5.5 PLL Frequency Synthesizer:
Changed "...to meet the power supply ripple standard" to "...within the acceptable range of power
supply ripple".
28.6.1 CPU Clock: Added line 2.
28.6.2 Wait Mode:
• Added lines 4 and 5 to the first bullet.
• Deleted second bullet in the previous version and added the second to fifth bullets.
28.6.3 Stop Mode:
• Added the last sentence to the third bullet.
• Deleted fifth bullet in the previous version and added fourth to ninth bullets.
28.6.4 Low Current Consumption Read Mode: Added the third bullet.
28.6.5 Slow Read Mode: Added.
28.7.2 Influence of SD :
• Changed the title from "Effect of SD Pin".
• Changed the explanation.
28.11 Notes on Timer A:
Rewritten by common items, and each mode.
28.12 Notes on Timer B:
Rewritten by common items, and each mode.
28.13.2 Influence of SD : Changed the title from "Forced Cutoff Input" and changed the explanation.
28.14.1 Register Access: Added.
28.14.2 Changing the G1IR Register: Changed the title from "G1IR Register", and changed the
explanation.
Figure 28.9 IC/OC Interrupt 0 Operation Example: Changed from "IC/OC Interrupt 0 and 1
Operation".
28.14.3 Changing Registers ICOCiIC (i = 0, 1): Changed from "Changing Registers ICOCiIC and
ICOCHjIC".
28.14.4 Output Waveform During the Base Timer Reset with the BTS bit and 28.14.5 OUTC1_0
Pin Output During the Base Timer Reset with the G1PO0 register: Changed from "Waveform
Generation Function".
28.14.6 Interrupt Request When Selecting Time Measurement Function: Added.
28.17.1 Common Notes on Multiple Modes: Added.
28.17.2.2 Transmission and 28.17.2.3 Reception:
Changed the style of the explanations about the external clock level into bulleted lists.
28.17.3.3 Setup and Hold Times When Generating a Start/Stop Condition to 28.17.3.6
Requirements to Start Transmission/Reception in Slave Mode: Added.
28.17.4 Special Mode 4 (SIM Mode):
Changed the conditions to generate a transmit interrupt request.
C- 15
Description
Summary
;DTA to t
;DAT and t
HD
HD
+-V
, which includes TA0IN and others in Hysteresis, from
T
T-
;DTA to t
;DAT and t
HD
HD
;DTA to t
;DAT.
su
su
;DTA to t
;DAT.
su
su
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