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M16C/5L Group, M16C/56 Group
IC/OC interrupt 0 processing
Buffer ← G1IR register
Wait for one fBT1 cycle
Bit i in the buffer is 1?
Set the G1IRi bit to 0
Channel i waveform generation
interrupt process
Bit j in the buffer is 1?
Set the G1IRj bit to 0
Channel j time measurement
interrupt process
Write 00h to the G1IE0 register
Set bits G1IE0i and G1IE0j to 1
i = 0 to 7; j = 0 to 7 (however, j and i cannot be the same value)
G1IRi, G1IRj: Bits in the G1IR register
G1IE0i, G1IE0j: Bits in the G1IE0 register
The above assumes the following:
With IC/OC interrupt 0, a waveform generation interrupt is processed for channel i, and a time measurement interrupt for channel j.
Interrupt requests for the other channels are disabled with the G1IE0 register.
Figure 18.20 IC/OC Interrupt 0 Operation Example
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
NO
YES
NO
YES
In this IC/OC interrupt 0 processing, when an interrupt request for channel i(j)
is generated after the processing to set the G1IRi (or G1IRj) bit to 0, the
G1IRi (G1IRj) bit remains 1. In this case, the IR bit remains 0, and the IC/OC
interrupt 0 request is not generated afterwards.
After disabling all the channels using the G1IE0 register, when the channels
are enabled again, if either the G1IRi bit or G1ITj bit is 1, the IR bit becomes
1, and the IC/OC interrupt 0 rquest is generated. Therefore a branch to the
End
IC/OC interrupt 0 processing is again made after returning from the interrupt
processing.
Store an interrupt request for each channel in the buffer on RAM.
Wait for one fBT1 cycle since the bits in the G1IR register
cannot be set to 0 for this period.
Check whether an interrupt request for channel i exists.
Clear the interrupt request for channel i.
Check whether an interrupt request for channel j exists.
Clear the interrupt request for channel j.
18. Timer S
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